1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * TI/National Semiconductor LP3943 Device 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2013 Texas Instruments 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Milo Kim <milo.kim@ti.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MFD_LP3943_H__ 11*4882a593Smuzhiyun #define __MFD_LP3943_H__ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/gpio.h> 14*4882a593Smuzhiyun #include <linux/pwm.h> 15*4882a593Smuzhiyun #include <linux/regmap.h> 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Registers */ 18*4882a593Smuzhiyun #define LP3943_REG_GPIO_A 0x00 19*4882a593Smuzhiyun #define LP3943_REG_GPIO_B 0x01 20*4882a593Smuzhiyun #define LP3943_REG_PRESCALE0 0x02 21*4882a593Smuzhiyun #define LP3943_REG_PWM0 0x03 22*4882a593Smuzhiyun #define LP3943_REG_PRESCALE1 0x04 23*4882a593Smuzhiyun #define LP3943_REG_PWM1 0x05 24*4882a593Smuzhiyun #define LP3943_REG_MUX0 0x06 25*4882a593Smuzhiyun #define LP3943_REG_MUX1 0x07 26*4882a593Smuzhiyun #define LP3943_REG_MUX2 0x08 27*4882a593Smuzhiyun #define LP3943_REG_MUX3 0x09 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* Bit description for LP3943_REG_MUX0 ~ 3 */ 30*4882a593Smuzhiyun #define LP3943_GPIO_IN 0x00 31*4882a593Smuzhiyun #define LP3943_GPIO_OUT_HIGH 0x00 32*4882a593Smuzhiyun #define LP3943_GPIO_OUT_LOW 0x01 33*4882a593Smuzhiyun #define LP3943_DIM_PWM0 0x02 34*4882a593Smuzhiyun #define LP3943_DIM_PWM1 0x03 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define LP3943_NUM_PWMS 2 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun enum lp3943_pwm_output { 39*4882a593Smuzhiyun LP3943_PWM_OUT0, 40*4882a593Smuzhiyun LP3943_PWM_OUT1, 41*4882a593Smuzhiyun LP3943_PWM_OUT2, 42*4882a593Smuzhiyun LP3943_PWM_OUT3, 43*4882a593Smuzhiyun LP3943_PWM_OUT4, 44*4882a593Smuzhiyun LP3943_PWM_OUT5, 45*4882a593Smuzhiyun LP3943_PWM_OUT6, 46*4882a593Smuzhiyun LP3943_PWM_OUT7, 47*4882a593Smuzhiyun LP3943_PWM_OUT8, 48*4882a593Smuzhiyun LP3943_PWM_OUT9, 49*4882a593Smuzhiyun LP3943_PWM_OUT10, 50*4882a593Smuzhiyun LP3943_PWM_OUT11, 51*4882a593Smuzhiyun LP3943_PWM_OUT12, 52*4882a593Smuzhiyun LP3943_PWM_OUT13, 53*4882a593Smuzhiyun LP3943_PWM_OUT14, 54*4882a593Smuzhiyun LP3943_PWM_OUT15, 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* 58*4882a593Smuzhiyun * struct lp3943_pwm_map 59*4882a593Smuzhiyun * @output: Output pins which are mapped to each PWM channel 60*4882a593Smuzhiyun * @num_outputs: Number of outputs 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun struct lp3943_pwm_map { 63*4882a593Smuzhiyun enum lp3943_pwm_output *output; 64*4882a593Smuzhiyun int num_outputs; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* 68*4882a593Smuzhiyun * struct lp3943_platform_data 69*4882a593Smuzhiyun * @pwms: Output channel definitions for PWM channel 0 and 1 70*4882a593Smuzhiyun */ 71*4882a593Smuzhiyun struct lp3943_platform_data { 72*4882a593Smuzhiyun struct lp3943_pwm_map *pwms[LP3943_NUM_PWMS]; 73*4882a593Smuzhiyun }; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* 76*4882a593Smuzhiyun * struct lp3943_reg_cfg 77*4882a593Smuzhiyun * @reg: Register address 78*4882a593Smuzhiyun * @mask: Register bit mask to be updated 79*4882a593Smuzhiyun * @shift: Register bit shift 80*4882a593Smuzhiyun */ 81*4882a593Smuzhiyun struct lp3943_reg_cfg { 82*4882a593Smuzhiyun u8 reg; 83*4882a593Smuzhiyun u8 mask; 84*4882a593Smuzhiyun u8 shift; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* 88*4882a593Smuzhiyun * struct lp3943 89*4882a593Smuzhiyun * @dev: Parent device pointer 90*4882a593Smuzhiyun * @regmap: Used for I2C communication on accessing registers 91*4882a593Smuzhiyun * @pdata: LP3943 platform specific data 92*4882a593Smuzhiyun * @mux_cfg: Register configuration for pin MUX 93*4882a593Smuzhiyun * @pin_used: Bit mask for output pin used. 94*4882a593Smuzhiyun * This bitmask is used for pin assignment management. 95*4882a593Smuzhiyun * 1 = pin used, 0 = available. 96*4882a593Smuzhiyun * Only LSB 16 bits are used, but it is unsigned long type 97*4882a593Smuzhiyun * for atomic bitwise operations. 98*4882a593Smuzhiyun */ 99*4882a593Smuzhiyun struct lp3943 { 100*4882a593Smuzhiyun struct device *dev; 101*4882a593Smuzhiyun struct regmap *regmap; 102*4882a593Smuzhiyun struct lp3943_platform_data *pdata; 103*4882a593Smuzhiyun const struct lp3943_reg_cfg *mux_cfg; 104*4882a593Smuzhiyun unsigned long pin_used; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun int lp3943_read_byte(struct lp3943 *lp3943, u8 reg, u8 *read); 108*4882a593Smuzhiyun int lp3943_write_byte(struct lp3943 *lp3943, u8 reg, u8 data); 109*4882a593Smuzhiyun int lp3943_update_bits(struct lp3943 *lp3943, u8 reg, u8 mask, u8 data); 110*4882a593Smuzhiyun #endif 111