1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Lochnagar2 register definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017-2018 Cirrus Logic, Inc. and 6*4882a593Smuzhiyun * Cirrus Logic International Semiconductor Ltd. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Charles Keepax <ckeepax@opensource.cirrus.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef LOCHNAGAR2_REGISTERS_H 12*4882a593Smuzhiyun #define LOCHNAGAR2_REGISTERS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Register Addresses */ 15*4882a593Smuzhiyun #define LOCHNAGAR2_CDC_AIF1_CTRL 0x000D 16*4882a593Smuzhiyun #define LOCHNAGAR2_CDC_AIF2_CTRL 0x000E 17*4882a593Smuzhiyun #define LOCHNAGAR2_CDC_AIF3_CTRL 0x000F 18*4882a593Smuzhiyun #define LOCHNAGAR2_DSP_AIF1_CTRL 0x0010 19*4882a593Smuzhiyun #define LOCHNAGAR2_DSP_AIF2_CTRL 0x0011 20*4882a593Smuzhiyun #define LOCHNAGAR2_PSIA1_CTRL 0x0012 21*4882a593Smuzhiyun #define LOCHNAGAR2_PSIA2_CTRL 0x0013 22*4882a593Smuzhiyun #define LOCHNAGAR2_GF_AIF3_CTRL 0x0014 23*4882a593Smuzhiyun #define LOCHNAGAR2_GF_AIF4_CTRL 0x0015 24*4882a593Smuzhiyun #define LOCHNAGAR2_GF_AIF1_CTRL 0x0016 25*4882a593Smuzhiyun #define LOCHNAGAR2_GF_AIF2_CTRL 0x0017 26*4882a593Smuzhiyun #define LOCHNAGAR2_SPDIF_AIF_CTRL 0x0018 27*4882a593Smuzhiyun #define LOCHNAGAR2_USB_AIF1_CTRL 0x0019 28*4882a593Smuzhiyun #define LOCHNAGAR2_USB_AIF2_CTRL 0x001A 29*4882a593Smuzhiyun #define LOCHNAGAR2_ADAT_AIF_CTRL 0x001B 30*4882a593Smuzhiyun #define LOCHNAGAR2_CDC_MCLK1_CTRL 0x001E 31*4882a593Smuzhiyun #define LOCHNAGAR2_CDC_MCLK2_CTRL 0x001F 32*4882a593Smuzhiyun #define LOCHNAGAR2_DSP_CLKIN_CTRL 0x0020 33*4882a593Smuzhiyun #define LOCHNAGAR2_PSIA1_MCLK_CTRL 0x0021 34*4882a593Smuzhiyun #define LOCHNAGAR2_PSIA2_MCLK_CTRL 0x0022 35*4882a593Smuzhiyun #define LOCHNAGAR2_SPDIF_MCLK_CTRL 0x0023 36*4882a593Smuzhiyun #define LOCHNAGAR2_GF_CLKOUT1_CTRL 0x0024 37*4882a593Smuzhiyun #define LOCHNAGAR2_GF_CLKOUT2_CTRL 0x0025 38*4882a593Smuzhiyun #define LOCHNAGAR2_ADAT_MCLK_CTRL 0x0026 39*4882a593Smuzhiyun #define LOCHNAGAR2_SOUNDCARD_MCLK_CTRL 0x0027 40*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_FPGA_GPIO1 0x0031 41*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_FPGA_GPIO2 0x0032 42*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_FPGA_GPIO3 0x0033 43*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_FPGA_GPIO4 0x0034 44*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_FPGA_GPIO5 0x0035 45*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_FPGA_GPIO6 0x0036 46*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_GPIO1 0x0037 47*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_GPIO2 0x0038 48*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_GPIO3 0x0039 49*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_GPIO4 0x003A 50*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_GPIO5 0x003B 51*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_GPIO6 0x003C 52*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_GPIO7 0x003D 53*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_GPIO8 0x003E 54*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_GPIO1 0x003F 55*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_GPIO2 0x0040 56*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_GPIO3 0x0041 57*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_GPIO4 0x0042 58*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_GPIO5 0x0043 59*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_GPIO6 0x0044 60*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_GPIO2 0x0045 61*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_GPIO3 0x0046 62*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_GPIO7 0x0047 63*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF1_BCLK 0x0048 64*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF1_RXDAT 0x0049 65*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF1_LRCLK 0x004A 66*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF1_TXDAT 0x004B 67*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF2_BCLK 0x004C 68*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF2_RXDAT 0x004D 69*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF2_LRCLK 0x004E 70*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF2_TXDAT 0x004F 71*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF3_BCLK 0x0050 72*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF3_RXDAT 0x0051 73*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF3_LRCLK 0x0052 74*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_AIF3_TXDAT 0x0053 75*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_AIF1_BCLK 0x0054 76*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_AIF1_RXDAT 0x0055 77*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_AIF1_LRCLK 0x0056 78*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_AIF1_TXDAT 0x0057 79*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_AIF2_BCLK 0x0058 80*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_AIF2_RXDAT 0x0059 81*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_AIF2_LRCLK 0x005A 82*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_AIF2_TXDAT 0x005B 83*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA1_BCLK 0x005C 84*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA1_RXDAT 0x005D 85*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA1_LRCLK 0x005E 86*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA1_TXDAT 0x005F 87*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA2_BCLK 0x0060 88*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA2_RXDAT 0x0061 89*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA2_LRCLK 0x0062 90*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA2_TXDAT 0x0063 91*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF3_BCLK 0x0064 92*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF3_RXDAT 0x0065 93*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF3_LRCLK 0x0066 94*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF3_TXDAT 0x0067 95*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF4_BCLK 0x0068 96*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF4_RXDAT 0x0069 97*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF4_LRCLK 0x006A 98*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF4_TXDAT 0x006B 99*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF1_BCLK 0x006C 100*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF1_RXDAT 0x006D 101*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF1_LRCLK 0x006E 102*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF1_TXDAT 0x006F 103*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF2_BCLK 0x0070 104*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF2_RXDAT 0x0071 105*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF2_LRCLK 0x0072 106*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_AIF2_TXDAT 0x0073 107*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_UART1_RX 0x0074 108*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_UART1_TX 0x0075 109*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_UART2_RX 0x0076 110*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_UART2_TX 0x0077 111*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_UART2_RX 0x0078 112*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_UART2_TX 0x0079 113*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_USB_UART_RX 0x007A 114*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_PDMCLK1 0x007C 115*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_PDMDAT1 0x007D 116*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_PDMCLK2 0x007E 117*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_PDMDAT2 0x007F 118*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_DMICCLK1 0x0080 119*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_DMICDAT1 0x0081 120*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_DMICCLK2 0x0082 121*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_DMICDAT2 0x0083 122*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_DMICCLK3 0x0084 123*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_DMICDAT3 0x0085 124*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_DMICCLK4 0x0086 125*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_DMICDAT4 0x0087 126*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_DMICCLK1 0x0088 127*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_DMICDAT1 0x0089 128*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_DMICCLK2 0x008A 129*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_DMICDAT2 0x008B 130*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_I2C2_SCL 0x008C 131*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_I2C2_SDA 0x008D 132*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_I2C3_SCL 0x008E 133*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_I2C3_SDA 0x008F 134*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_I2C4_SCL 0x0090 135*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_I2C4_SDA 0x0091 136*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_STANDBY 0x0092 137*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_MCLK1 0x0093 138*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CDC_MCLK2 0x0094 139*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_CLKIN 0x0095 140*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA1_MCLK 0x0096 141*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_PSIA2_MCLK 0x0097 142*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_GPIO1 0x0098 143*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_GF_GPIO5 0x0099 144*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_DSP_GPIO20 0x009A 145*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL1 0x00B9 146*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL2 0x00BA 147*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL3 0x00BB 148*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL4 0x00BC 149*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL5 0x00BD 150*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL6 0x00BE 151*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL7 0x00BF 152*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL8 0x00C0 153*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL9 0x00C1 154*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL10 0x00C2 155*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL11 0x00C3 156*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL12 0x00C4 157*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL13 0x00C5 158*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL14 0x00C6 159*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL15 0x00C7 160*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL16 0x00C8 161*4882a593Smuzhiyun #define LOCHNAGAR2_MINICARD_RESETS 0x00DF 162*4882a593Smuzhiyun #define LOCHNAGAR2_ANALOGUE_PATH_CTRL1 0x00E3 163*4882a593Smuzhiyun #define LOCHNAGAR2_ANALOGUE_PATH_CTRL2 0x00E4 164*4882a593Smuzhiyun #define LOCHNAGAR2_COMMS_CTRL4 0x00F0 165*4882a593Smuzhiyun #define LOCHNAGAR2_SPDIF_CTRL 0x00FE 166*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CTRL1 0x0108 167*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CTRL2 0x0109 168*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CTRL3 0x010A 169*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CTRL4 0x010B 170*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DATA1 0x010C 171*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DATA2 0x010D 172*4882a593Smuzhiyun #define LOCHNAGAR2_POWER_CTRL 0x0116 173*4882a593Smuzhiyun #define LOCHNAGAR2_MICVDD_CTRL1 0x0119 174*4882a593Smuzhiyun #define LOCHNAGAR2_MICVDD_CTRL2 0x011B 175*4882a593Smuzhiyun #define LOCHNAGAR2_VDDCORE_CDC_CTRL1 0x011E 176*4882a593Smuzhiyun #define LOCHNAGAR2_VDDCORE_CDC_CTRL2 0x0120 177*4882a593Smuzhiyun #define LOCHNAGAR2_SOUNDCARD_AIF_CTRL 0x0180 178*4882a593Smuzhiyun 179*4882a593Smuzhiyun /* (0x000D-0x001B, 0x0180) CDC_AIF1_CTRL - SOUNCARD_AIF_CTRL */ 180*4882a593Smuzhiyun #define LOCHNAGAR2_AIF_ENA_MASK 0x8000 181*4882a593Smuzhiyun #define LOCHNAGAR2_AIF_ENA_SHIFT 15 182*4882a593Smuzhiyun #define LOCHNAGAR2_AIF_LRCLK_DIR_MASK 0x4000 183*4882a593Smuzhiyun #define LOCHNAGAR2_AIF_LRCLK_DIR_SHIFT 14 184*4882a593Smuzhiyun #define LOCHNAGAR2_AIF_BCLK_DIR_MASK 0x2000 185*4882a593Smuzhiyun #define LOCHNAGAR2_AIF_BCLK_DIR_SHIFT 13 186*4882a593Smuzhiyun #define LOCHNAGAR2_AIF_SRC_MASK 0x00FF 187*4882a593Smuzhiyun #define LOCHNAGAR2_AIF_SRC_SHIFT 0 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun /* (0x001E - 0x0027) CDC_MCLK1_CTRL - SOUNDCARD_MCLK_CTRL */ 190*4882a593Smuzhiyun #define LOCHNAGAR2_CLK_ENA_MASK 0x8000 191*4882a593Smuzhiyun #define LOCHNAGAR2_CLK_ENA_SHIFT 15 192*4882a593Smuzhiyun #define LOCHNAGAR2_CLK_SRC_MASK 0x00FF 193*4882a593Smuzhiyun #define LOCHNAGAR2_CLK_SRC_SHIFT 0 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun /* (0x0031 - 0x009A) GPIO_FPGA_GPIO1 - GPIO_DSP_GPIO20 */ 196*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_SRC_MASK 0x00FF 197*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_SRC_SHIFT 0 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* (0x00B9 - 0x00C8) GPIO_CHANNEL1 - GPIO_CHANNEL16 */ 200*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL_STS_MASK 0x8000 201*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL_STS_SHIFT 15 202*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL_SRC_MASK 0x00FF 203*4882a593Smuzhiyun #define LOCHNAGAR2_GPIO_CHANNEL_SRC_SHIFT 0 204*4882a593Smuzhiyun 205*4882a593Smuzhiyun /* (0x00DF) MINICARD_RESETS */ 206*4882a593Smuzhiyun #define LOCHNAGAR2_DSP_RESET_MASK 0x0002 207*4882a593Smuzhiyun #define LOCHNAGAR2_DSP_RESET_SHIFT 1 208*4882a593Smuzhiyun #define LOCHNAGAR2_CDC_RESET_MASK 0x0001 209*4882a593Smuzhiyun #define LOCHNAGAR2_CDC_RESET_SHIFT 0 210*4882a593Smuzhiyun 211*4882a593Smuzhiyun /* (0x00E3) ANALOGUE_PATH_CTRL1 */ 212*4882a593Smuzhiyun #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_MASK 0x8000 213*4882a593Smuzhiyun #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_SHIFT 15 214*4882a593Smuzhiyun #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_MASK 0x4000 215*4882a593Smuzhiyun #define LOCHNAGAR2_ANALOGUE_PATH_UPDATE_STS_SHIFT 14 216*4882a593Smuzhiyun 217*4882a593Smuzhiyun /* (0x00E4) ANALOGUE_PATH_CTRL2 */ 218*4882a593Smuzhiyun #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_MASK 0x0080 219*4882a593Smuzhiyun #define LOCHNAGAR2_P2_INPUT_BIAS_ENA_SHIFT 7 220*4882a593Smuzhiyun #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_MASK 0x0040 221*4882a593Smuzhiyun #define LOCHNAGAR2_P1_INPUT_BIAS_ENA_SHIFT 6 222*4882a593Smuzhiyun #define LOCHNAGAR2_P2_MICBIAS_SRC_MASK 0x0038 223*4882a593Smuzhiyun #define LOCHNAGAR2_P2_MICBIAS_SRC_SHIFT 3 224*4882a593Smuzhiyun #define LOCHNAGAR2_P1_MICBIAS_SRC_MASK 0x0007 225*4882a593Smuzhiyun #define LOCHNAGAR2_P1_MICBIAS_SRC_SHIFT 0 226*4882a593Smuzhiyun 227*4882a593Smuzhiyun /* (0x00F0) COMMS_CTRL4 */ 228*4882a593Smuzhiyun #define LOCHNAGAR2_CDC_CIF1MODE_MASK 0x0001 229*4882a593Smuzhiyun #define LOCHNAGAR2_CDC_CIF1MODE_SHIFT 0 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* (0x00FE) SPDIF_CTRL */ 232*4882a593Smuzhiyun #define LOCHNAGAR2_SPDIF_HWMODE_MASK 0x0008 233*4882a593Smuzhiyun #define LOCHNAGAR2_SPDIF_HWMODE_SHIFT 3 234*4882a593Smuzhiyun #define LOCHNAGAR2_SPDIF_RESET_MASK 0x0001 235*4882a593Smuzhiyun #define LOCHNAGAR2_SPDIF_RESET_SHIFT 0 236*4882a593Smuzhiyun 237*4882a593Smuzhiyun /* (0x0108) IMON_CTRL1 */ 238*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_ENA_MASK 0x8000 239*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_ENA_SHIFT 15 240*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_MASK 0x03FC 241*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_MEASURED_CHANNELS_SHIFT 2 242*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_MODE_SEL_MASK 0x0003 243*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_MODE_SEL_SHIFT 0 244*4882a593Smuzhiyun 245*4882a593Smuzhiyun /* (0x0109) IMON_CTRL2 */ 246*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_FSR_MASK 0x03FF 247*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_FSR_SHIFT 0 248*4882a593Smuzhiyun 249*4882a593Smuzhiyun /* (0x010A) IMON_CTRL3 */ 250*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DONE_MASK 0x0004 251*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DONE_SHIFT 2 252*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CONFIGURE_MASK 0x0002 253*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CONFIGURE_SHIFT 1 254*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_MEASURE_MASK 0x0001 255*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_MEASURE_SHIFT 0 256*4882a593Smuzhiyun 257*4882a593Smuzhiyun /* (0x010B) IMON_CTRL4 */ 258*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DATA_REQ_MASK 0x0080 259*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DATA_REQ_SHIFT 7 260*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CH_SEL_MASK 0x0070 261*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CH_SEL_SHIFT 4 262*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DATA_RDY_MASK 0x0008 263*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DATA_RDY_SHIFT 3 264*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CH_SRC_MASK 0x0007 265*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_CH_SRC_SHIFT 0 266*4882a593Smuzhiyun 267*4882a593Smuzhiyun /* (0x010C, 0x010D) IMON_DATA1, IMON_DATA2 */ 268*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DATA_MASK 0xFFFF 269*4882a593Smuzhiyun #define LOCHNAGAR2_IMON_DATA_SHIFT 0 270*4882a593Smuzhiyun 271*4882a593Smuzhiyun /* (0x0116) POWER_CTRL */ 272*4882a593Smuzhiyun #define LOCHNAGAR2_PWR_ENA_MASK 0x0001 273*4882a593Smuzhiyun #define LOCHNAGAR2_PWR_ENA_SHIFT 0 274*4882a593Smuzhiyun 275*4882a593Smuzhiyun /* (0x0119) MICVDD_CTRL1 */ 276*4882a593Smuzhiyun #define LOCHNAGAR2_MICVDD_REG_ENA_MASK 0x8000 277*4882a593Smuzhiyun #define LOCHNAGAR2_MICVDD_REG_ENA_SHIFT 15 278*4882a593Smuzhiyun 279*4882a593Smuzhiyun /* (0x011B) MICVDD_CTRL2 */ 280*4882a593Smuzhiyun #define LOCHNAGAR2_MICVDD_VSEL_MASK 0x001F 281*4882a593Smuzhiyun #define LOCHNAGAR2_MICVDD_VSEL_SHIFT 0 282*4882a593Smuzhiyun 283*4882a593Smuzhiyun /* (0x011E) VDDCORE_CDC_CTRL1 */ 284*4882a593Smuzhiyun #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_MASK 0x8000 285*4882a593Smuzhiyun #define LOCHNAGAR2_VDDCORE_CDC_REG_ENA_SHIFT 15 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* (0x0120) VDDCORE_CDC_CTRL2 */ 288*4882a593Smuzhiyun #define LOCHNAGAR2_VDDCORE_CDC_VSEL_MASK 0x007F 289*4882a593Smuzhiyun #define LOCHNAGAR2_VDDCORE_CDC_VSEL_SHIFT 0 290*4882a593Smuzhiyun 291*4882a593Smuzhiyun #endif 292