1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Lochnagar1 register definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2017-2018 Cirrus Logic, Inc. and 6*4882a593Smuzhiyun * Cirrus Logic International Semiconductor Ltd. 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Author: Charles Keepax <ckeepax@opensource.cirrus.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef LOCHNAGAR1_REGISTERS_H 12*4882a593Smuzhiyun #define LOCHNAGAR1_REGISTERS_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Register Addresses */ 15*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF1_SEL 0x0008 16*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF2_SEL 0x0009 17*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF3_SEL 0x000A 18*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_MCLK1_SEL 0x000B 19*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_MCLK2_SEL 0x000C 20*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF_CTRL1 0x000D 21*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF_CTRL2 0x000E 22*4882a593Smuzhiyun #define LOCHNAGAR1_EXT_AIF_CTRL 0x000F 23*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF1_SEL 0x0010 24*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF2_SEL 0x0011 25*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_CLKIN_SEL 0x0012 26*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF 0x0013 27*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF1 0x0014 28*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF2 0x0015 29*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA_AIF 0x0016 30*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA1_SEL 0x0017 31*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA2_SEL 0x0018 32*4882a593Smuzhiyun #define LOCHNAGAR1_SPDIF_AIF_SEL 0x0019 33*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF3_SEL 0x001C 34*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF4_SEL 0x001D 35*4882a593Smuzhiyun #define LOCHNAGAR1_GF_CLKOUT1_SEL 0x001E 36*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF1_SEL 0x001F 37*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF2_SEL 0x0020 38*4882a593Smuzhiyun #define LOCHNAGAR1_GF_GPIO2 0x0026 39*4882a593Smuzhiyun #define LOCHNAGAR1_GF_GPIO3 0x0027 40*4882a593Smuzhiyun #define LOCHNAGAR1_GF_GPIO7 0x0028 41*4882a593Smuzhiyun #define LOCHNAGAR1_RST 0x0029 42*4882a593Smuzhiyun #define LOCHNAGAR1_LED1 0x002A 43*4882a593Smuzhiyun #define LOCHNAGAR1_LED2 0x002B 44*4882a593Smuzhiyun #define LOCHNAGAR1_I2C_CTRL 0x0046 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * (0x0008 - 0x000C, 0x0010 - 0x0012, 0x0017 - 0x0020) 48*4882a593Smuzhiyun * CDC_AIF1_SEL - GF_AIF2_SEL 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun #define LOCHNAGAR1_SRC_MASK 0xFF 51*4882a593Smuzhiyun #define LOCHNAGAR1_SRC_SHIFT 0 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* (0x000D) CDC_AIF_CTRL1 */ 54*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_MASK 0x40 55*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF2_LRCLK_DIR_SHIFT 6 56*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_MASK 0x20 57*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF2_BCLK_DIR_SHIFT 5 58*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF2_ENA_MASK 0x10 59*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF2_ENA_SHIFT 4 60*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_MASK 0x04 61*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF1_LRCLK_DIR_SHIFT 2 62*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_MASK 0x02 63*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF1_BCLK_DIR_SHIFT 1 64*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF1_ENA_MASK 0x01 65*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF1_ENA_SHIFT 0 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* (0x000E) CDC_AIF_CTRL2 */ 68*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_MASK 0x40 69*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF3_LRCLK_DIR_SHIFT 6 70*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_MASK 0x20 71*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF3_BCLK_DIR_SHIFT 5 72*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF3_ENA_MASK 0x10 73*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_AIF3_ENA_SHIFT 4 74*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_MCLK1_ENA_MASK 0x02 75*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_MCLK1_ENA_SHIFT 1 76*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_MCLK2_ENA_MASK 0x01 77*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_MCLK2_ENA_SHIFT 0 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun /* (0x000F) EXT_AIF_CTRL */ 80*4882a593Smuzhiyun #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_MASK 0x20 81*4882a593Smuzhiyun #define LOCHNAGAR1_SPDIF_AIF_LRCLK_DIR_SHIFT 5 82*4882a593Smuzhiyun #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_MASK 0x10 83*4882a593Smuzhiyun #define LOCHNAGAR1_SPDIF_AIF_BCLK_DIR_SHIFT 4 84*4882a593Smuzhiyun #define LOCHNAGAR1_SPDIF_AIF_ENA_MASK 0x08 85*4882a593Smuzhiyun #define LOCHNAGAR1_SPDIF_AIF_ENA_SHIFT 3 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* (0x0013) DSP_AIF */ 88*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_MASK 0x40 89*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF2_LRCLK_DIR_SHIFT 6 90*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_MASK 0x20 91*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF2_BCLK_DIR_SHIFT 5 92*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF2_ENA_MASK 0x10 93*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF2_ENA_SHIFT 4 94*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_CLKIN_ENA_MASK 0x08 95*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_CLKIN_ENA_SHIFT 3 96*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_MASK 0x04 97*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF1_LRCLK_DIR_SHIFT 2 98*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_MASK 0x02 99*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF1_BCLK_DIR_SHIFT 1 100*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF1_ENA_MASK 0x01 101*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_AIF1_ENA_SHIFT 0 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun /* (0x0014) GF_AIF1 */ 104*4882a593Smuzhiyun #define LOCHNAGAR1_GF_CLKOUT1_ENA_MASK 0x40 105*4882a593Smuzhiyun #define LOCHNAGAR1_GF_CLKOUT1_ENA_SHIFT 6 106*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_MASK 0x20 107*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF3_LRCLK_DIR_SHIFT 5 108*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_MASK 0x10 109*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF3_BCLK_DIR_SHIFT 4 110*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF3_ENA_MASK 0x08 111*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF3_ENA_SHIFT 3 112*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_MASK 0x04 113*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF1_LRCLK_DIR_SHIFT 2 114*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_MASK 0x02 115*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF1_BCLK_DIR_SHIFT 1 116*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF1_ENA_MASK 0x01 117*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF1_ENA_SHIFT 0 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* (0x0015) GF_AIF2 */ 120*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_MASK 0x20 121*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF4_LRCLK_DIR_SHIFT 5 122*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_MASK 0x10 123*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF4_BCLK_DIR_SHIFT 4 124*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF4_ENA_MASK 0x08 125*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF4_ENA_SHIFT 3 126*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_MASK 0x04 127*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF2_LRCLK_DIR_SHIFT 2 128*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_MASK 0x02 129*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF2_BCLK_DIR_SHIFT 1 130*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF2_ENA_MASK 0x01 131*4882a593Smuzhiyun #define LOCHNAGAR1_GF_AIF2_ENA_SHIFT 0 132*4882a593Smuzhiyun 133*4882a593Smuzhiyun /* (0x0016) PSIA_AIF */ 134*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA2_LRCLK_DIR_MASK 0x40 135*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA2_LRCLK_DIR_SHIFT 6 136*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA2_BCLK_DIR_MASK 0x20 137*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA2_BCLK_DIR_SHIFT 5 138*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA2_ENA_MASK 0x10 139*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA2_ENA_SHIFT 4 140*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA1_LRCLK_DIR_MASK 0x04 141*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA1_LRCLK_DIR_SHIFT 2 142*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA1_BCLK_DIR_MASK 0x02 143*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA1_BCLK_DIR_SHIFT 1 144*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA1_ENA_MASK 0x01 145*4882a593Smuzhiyun #define LOCHNAGAR1_PSIA1_ENA_SHIFT 0 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* (0x0029) RST */ 148*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_RESET_MASK 0x02 149*4882a593Smuzhiyun #define LOCHNAGAR1_DSP_RESET_SHIFT 1 150*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_RESET_MASK 0x01 151*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_RESET_SHIFT 0 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* (0x0046) I2C_CTRL */ 154*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_CIF_MODE_MASK 0x01 155*4882a593Smuzhiyun #define LOCHNAGAR1_CDC_CIF_MODE_SHIFT 0 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun #endif 158