xref: /OK3568_Linux_fs/kernel/include/linux/mfd/iqs62x.h (revision 4882a59341e53eb6f0b4789bf948001014eff981) 
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Azoteq IQS620A/621/622/624/625 Multi-Function Sensors
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2019 Jeff LaBundy <jeff@labundy.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __LINUX_MFD_IQS62X_H
9*4882a593Smuzhiyun #define __LINUX_MFD_IQS62X_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #define IQS620_PROD_NUM				0x41
12*4882a593Smuzhiyun #define IQS621_PROD_NUM				0x46
13*4882a593Smuzhiyun #define IQS622_PROD_NUM				0x42
14*4882a593Smuzhiyun #define IQS624_PROD_NUM				0x43
15*4882a593Smuzhiyun #define IQS625_PROD_NUM				0x4E
16*4882a593Smuzhiyun 
17*4882a593Smuzhiyun #define IQS621_ALS_FLAGS			0x16
18*4882a593Smuzhiyun #define IQS622_ALS_FLAGS			0x14
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define IQS624_HALL_UI				0x70
21*4882a593Smuzhiyun #define IQS624_HALL_UI_WHL_EVENT		BIT(4)
22*4882a593Smuzhiyun #define IQS624_HALL_UI_INT_EVENT		BIT(3)
23*4882a593Smuzhiyun #define IQS624_HALL_UI_AUTO_CAL			BIT(2)
24*4882a593Smuzhiyun 
25*4882a593Smuzhiyun #define IQS624_INTERVAL_DIV			0x7D
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define IQS620_GLBL_EVENT_MASK			0xD7
28*4882a593Smuzhiyun #define IQS620_GLBL_EVENT_MASK_PMU		BIT(6)
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun #define IQS62X_NUM_KEYS				16
31*4882a593Smuzhiyun #define IQS62X_NUM_EVENTS			(IQS62X_NUM_KEYS + 5)
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #define IQS62X_EVENT_SIZE			10
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun enum iqs62x_ui_sel {
36*4882a593Smuzhiyun 	IQS62X_UI_PROX,
37*4882a593Smuzhiyun 	IQS62X_UI_SAR1,
38*4882a593Smuzhiyun };
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun enum iqs62x_event_reg {
41*4882a593Smuzhiyun 	IQS62X_EVENT_NONE,
42*4882a593Smuzhiyun 	IQS62X_EVENT_SYS,
43*4882a593Smuzhiyun 	IQS62X_EVENT_PROX,
44*4882a593Smuzhiyun 	IQS62X_EVENT_HYST,
45*4882a593Smuzhiyun 	IQS62X_EVENT_HALL,
46*4882a593Smuzhiyun 	IQS62X_EVENT_ALS,
47*4882a593Smuzhiyun 	IQS62X_EVENT_IR,
48*4882a593Smuzhiyun 	IQS62X_EVENT_WHEEL,
49*4882a593Smuzhiyun 	IQS62X_EVENT_INTER,
50*4882a593Smuzhiyun 	IQS62X_EVENT_UI_LO,
51*4882a593Smuzhiyun 	IQS62X_EVENT_UI_HI,
52*4882a593Smuzhiyun };
53*4882a593Smuzhiyun 
54*4882a593Smuzhiyun enum iqs62x_event_flag {
55*4882a593Smuzhiyun 	/* keys */
56*4882a593Smuzhiyun 	IQS62X_EVENT_PROX_CH0_T,
57*4882a593Smuzhiyun 	IQS62X_EVENT_PROX_CH0_P,
58*4882a593Smuzhiyun 	IQS62X_EVENT_PROX_CH1_T,
59*4882a593Smuzhiyun 	IQS62X_EVENT_PROX_CH1_P,
60*4882a593Smuzhiyun 	IQS62X_EVENT_PROX_CH2_T,
61*4882a593Smuzhiyun 	IQS62X_EVENT_PROX_CH2_P,
62*4882a593Smuzhiyun 	IQS62X_EVENT_HYST_POS_T,
63*4882a593Smuzhiyun 	IQS62X_EVENT_HYST_POS_P,
64*4882a593Smuzhiyun 	IQS62X_EVENT_HYST_NEG_T,
65*4882a593Smuzhiyun 	IQS62X_EVENT_HYST_NEG_P,
66*4882a593Smuzhiyun 	IQS62X_EVENT_SAR1_ACT,
67*4882a593Smuzhiyun 	IQS62X_EVENT_SAR1_QRD,
68*4882a593Smuzhiyun 	IQS62X_EVENT_SAR1_MOVE,
69*4882a593Smuzhiyun 	IQS62X_EVENT_SAR1_HALT,
70*4882a593Smuzhiyun 	IQS62X_EVENT_WHEEL_UP,
71*4882a593Smuzhiyun 	IQS62X_EVENT_WHEEL_DN,
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun 	/* switches */
74*4882a593Smuzhiyun 	IQS62X_EVENT_HALL_N_T,
75*4882a593Smuzhiyun 	IQS62X_EVENT_HALL_N_P,
76*4882a593Smuzhiyun 	IQS62X_EVENT_HALL_S_T,
77*4882a593Smuzhiyun 	IQS62X_EVENT_HALL_S_P,
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/* everything else */
80*4882a593Smuzhiyun 	IQS62X_EVENT_SYS_RESET,
81*4882a593Smuzhiyun };
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun struct iqs62x_event_data {
84*4882a593Smuzhiyun 	u16 ui_data;
85*4882a593Smuzhiyun 	u8 als_flags;
86*4882a593Smuzhiyun 	u8 ir_flags;
87*4882a593Smuzhiyun 	u8 interval;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun 
90*4882a593Smuzhiyun struct iqs62x_event_desc {
91*4882a593Smuzhiyun 	enum iqs62x_event_reg reg;
92*4882a593Smuzhiyun 	u8 mask;
93*4882a593Smuzhiyun 	u8 val;
94*4882a593Smuzhiyun };
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun struct iqs62x_dev_desc {
97*4882a593Smuzhiyun 	const char *dev_name;
98*4882a593Smuzhiyun 	const struct mfd_cell *sub_devs;
99*4882a593Smuzhiyun 	int num_sub_devs;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	u8 prod_num;
102*4882a593Smuzhiyun 	u8 sw_num;
103*4882a593Smuzhiyun 	const u8 *cal_regs;
104*4882a593Smuzhiyun 	int num_cal_regs;
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun 	u8 prox_mask;
107*4882a593Smuzhiyun 	u8 sar_mask;
108*4882a593Smuzhiyun 	u8 hall_mask;
109*4882a593Smuzhiyun 	u8 hyst_mask;
110*4882a593Smuzhiyun 	u8 temp_mask;
111*4882a593Smuzhiyun 	u8 als_mask;
112*4882a593Smuzhiyun 	u8 ir_mask;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	u8 prox_settings;
115*4882a593Smuzhiyun 	u8 als_flags;
116*4882a593Smuzhiyun 	u8 hall_flags;
117*4882a593Smuzhiyun 	u8 hyst_shift;
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun 	u8 interval;
120*4882a593Smuzhiyun 	u8 interval_div;
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	u8 clk_div;
123*4882a593Smuzhiyun 	const char *fw_name;
124*4882a593Smuzhiyun 	const enum iqs62x_event_reg (*event_regs)[IQS62X_EVENT_SIZE];
125*4882a593Smuzhiyun };
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun struct iqs62x_core {
128*4882a593Smuzhiyun 	const struct iqs62x_dev_desc *dev_desc;
129*4882a593Smuzhiyun 	struct i2c_client *client;
130*4882a593Smuzhiyun 	struct regmap *regmap;
131*4882a593Smuzhiyun 	struct blocking_notifier_head nh;
132*4882a593Smuzhiyun 	struct list_head fw_blk_head;
133*4882a593Smuzhiyun 	struct completion fw_done;
134*4882a593Smuzhiyun 	enum iqs62x_ui_sel ui_sel;
135*4882a593Smuzhiyun };
136*4882a593Smuzhiyun 
137*4882a593Smuzhiyun extern const struct iqs62x_event_desc iqs62x_events[IQS62X_NUM_EVENTS];
138*4882a593Smuzhiyun 
139*4882a593Smuzhiyun #endif /* __LINUX_MFD_IQS62X_H */
140