1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header file for Intel Merrifield Basin Cove PMIC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2019 Intel Corporation. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __INTEL_SOC_PMIC_MRFLD_H__ 9*4882a593Smuzhiyun #define __INTEL_SOC_PMIC_MRFLD_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include <linux/bits.h> 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #define BCOVE_ID 0x00 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define BCOVE_ID_MINREV0 GENMASK(2, 0) 16*4882a593Smuzhiyun #define BCOVE_ID_MAJREV0 GENMASK(5, 3) 17*4882a593Smuzhiyun #define BCOVE_ID_VENDID0 GENMASK(7, 6) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define BCOVE_MINOR(x) (unsigned int)(((x) & BCOVE_ID_MINREV0) >> 0) 20*4882a593Smuzhiyun #define BCOVE_MAJOR(x) (unsigned int)(((x) & BCOVE_ID_MAJREV0) >> 3) 21*4882a593Smuzhiyun #define BCOVE_VENDOR(x) (unsigned int)(((x) & BCOVE_ID_VENDID0) >> 6) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define BCOVE_IRQLVL1 0x01 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #define BCOVE_PBIRQ 0x02 26*4882a593Smuzhiyun #define BCOVE_TMUIRQ 0x03 27*4882a593Smuzhiyun #define BCOVE_THRMIRQ 0x04 28*4882a593Smuzhiyun #define BCOVE_BCUIRQ 0x05 29*4882a593Smuzhiyun #define BCOVE_ADCIRQ 0x06 30*4882a593Smuzhiyun #define BCOVE_CHGRIRQ0 0x07 31*4882a593Smuzhiyun #define BCOVE_CHGRIRQ1 0x08 32*4882a593Smuzhiyun #define BCOVE_GPIOIRQ 0x09 33*4882a593Smuzhiyun #define BCOVE_CRITIRQ 0x0B 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define BCOVE_MIRQLVL1 0x0C 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define BCOVE_MPBIRQ 0x0D 38*4882a593Smuzhiyun #define BCOVE_MTMUIRQ 0x0E 39*4882a593Smuzhiyun #define BCOVE_MTHRMIRQ 0x0F 40*4882a593Smuzhiyun #define BCOVE_MBCUIRQ 0x10 41*4882a593Smuzhiyun #define BCOVE_MADCIRQ 0x11 42*4882a593Smuzhiyun #define BCOVE_MCHGRIRQ0 0x12 43*4882a593Smuzhiyun #define BCOVE_MCHGRIRQ1 0x13 44*4882a593Smuzhiyun #define BCOVE_MGPIOIRQ 0x14 45*4882a593Smuzhiyun #define BCOVE_MCRITIRQ 0x16 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define BCOVE_SCHGRIRQ0 0x4E 48*4882a593Smuzhiyun #define BCOVE_SCHGRIRQ1 0x4F 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Level 1 IRQs */ 51*4882a593Smuzhiyun #define BCOVE_LVL1_PWRBTN BIT(0) /* power button */ 52*4882a593Smuzhiyun #define BCOVE_LVL1_TMU BIT(1) /* time management unit */ 53*4882a593Smuzhiyun #define BCOVE_LVL1_THRM BIT(2) /* thermal */ 54*4882a593Smuzhiyun #define BCOVE_LVL1_BCU BIT(3) /* burst control unit */ 55*4882a593Smuzhiyun #define BCOVE_LVL1_ADC BIT(4) /* ADC */ 56*4882a593Smuzhiyun #define BCOVE_LVL1_CHGR BIT(5) /* charger */ 57*4882a593Smuzhiyun #define BCOVE_LVL1_GPIO BIT(6) /* GPIO */ 58*4882a593Smuzhiyun #define BCOVE_LVL1_CRIT BIT(7) /* critical event */ 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun /* Level 2 IRQs: power button */ 61*4882a593Smuzhiyun #define BCOVE_PBIRQ_PBTN BIT(0) 62*4882a593Smuzhiyun #define BCOVE_PBIRQ_UBTN BIT(1) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* Level 2 IRQs: ADC */ 65*4882a593Smuzhiyun #define BCOVE_ADCIRQ_BATTEMP BIT(2) 66*4882a593Smuzhiyun #define BCOVE_ADCIRQ_SYSTEMP BIT(3) 67*4882a593Smuzhiyun #define BCOVE_ADCIRQ_BATTID BIT(4) 68*4882a593Smuzhiyun #define BCOVE_ADCIRQ_VIBATT BIT(5) 69*4882a593Smuzhiyun #define BCOVE_ADCIRQ_CCTICK BIT(7) 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* Level 2 IRQs: charger */ 72*4882a593Smuzhiyun #define BCOVE_CHGRIRQ_BAT0ALRT BIT(4) 73*4882a593Smuzhiyun #define BCOVE_CHGRIRQ_BAT1ALRT BIT(5) 74*4882a593Smuzhiyun #define BCOVE_CHGRIRQ_BATCRIT BIT(6) 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define BCOVE_CHGRIRQ_VBUSDET BIT(0) 77*4882a593Smuzhiyun #define BCOVE_CHGRIRQ_DCDET BIT(1) 78*4882a593Smuzhiyun #define BCOVE_CHGRIRQ_BATTDET BIT(2) 79*4882a593Smuzhiyun #define BCOVE_CHGRIRQ_USBIDDET BIT(3) 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #endif /* __INTEL_SOC_PMIC_MRFLD_H__ */ 82