1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header file for Intel Broxton Whiskey Cove PMIC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2015 Intel Corporation. All rights reserved. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __INTEL_BXTWC_H__ 9*4882a593Smuzhiyun #define __INTEL_BXTWC_H__ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* BXT WC devices */ 12*4882a593Smuzhiyun #define BXTWC_DEVICE1_ADDR 0x4E 13*4882a593Smuzhiyun #define BXTWC_DEVICE2_ADDR 0x4F 14*4882a593Smuzhiyun #define BXTWC_DEVICE3_ADDR 0x5E 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* device1 Registers */ 17*4882a593Smuzhiyun #define BXTWC_CHIPID 0x4E00 18*4882a593Smuzhiyun #define BXTWC_CHIPVER 0x4E01 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun #define BXTWC_SCHGRIRQ0_ADDR 0x5E1A 21*4882a593Smuzhiyun #define BXTWC_CHGRCTRL0_ADDR 0x5E16 22*4882a593Smuzhiyun #define BXTWC_CHGRCTRL1_ADDR 0x5E17 23*4882a593Smuzhiyun #define BXTWC_CHGRCTRL2_ADDR 0x5E18 24*4882a593Smuzhiyun #define BXTWC_CHGRSTATUS_ADDR 0x5E19 25*4882a593Smuzhiyun #define BXTWC_THRMBATZONE_ADDR 0x4F22 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define BXTWC_USBPATH_ADDR 0x5E19 28*4882a593Smuzhiyun #define BXTWC_USBPHYCTRL_ADDR 0x5E07 29*4882a593Smuzhiyun #define BXTWC_USBIDCTRL_ADDR 0x5E05 30*4882a593Smuzhiyun #define BXTWC_USBIDEN_MASK 0x01 31*4882a593Smuzhiyun #define BXTWC_USBIDSTAT_ADDR 0x00FF 32*4882a593Smuzhiyun #define BXTWC_USBSRCDETSTATUS_ADDR 0x5E29 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define BXTWC_DBGUSBBC1_ADDR 0x5FE0 35*4882a593Smuzhiyun #define BXTWC_DBGUSBBC2_ADDR 0x5FE1 36*4882a593Smuzhiyun #define BXTWC_DBGUSBBCSTAT_ADDR 0x5FE2 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #define BXTWC_WAKESRC_ADDR 0x4E22 39*4882a593Smuzhiyun #define BXTWC_WAKESRC2_ADDR 0x4EE5 40*4882a593Smuzhiyun #define BXTWC_CHRTTADDR_ADDR 0x5E22 41*4882a593Smuzhiyun #define BXTWC_CHRTTDATA_ADDR 0x5E23 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define BXTWC_STHRMIRQ0_ADDR 0x4F19 44*4882a593Smuzhiyun #define WC_MTHRMIRQ1_ADDR 0x4E12 45*4882a593Smuzhiyun #define WC_STHRMIRQ1_ADDR 0x4F1A 46*4882a593Smuzhiyun #define WC_STHRMIRQ2_ADDR 0x4F1B 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define BXTWC_THRMZN0H_ADDR 0x4F44 49*4882a593Smuzhiyun #define BXTWC_THRMZN0L_ADDR 0x4F45 50*4882a593Smuzhiyun #define BXTWC_THRMZN1H_ADDR 0x4F46 51*4882a593Smuzhiyun #define BXTWC_THRMZN1L_ADDR 0x4F47 52*4882a593Smuzhiyun #define BXTWC_THRMZN2H_ADDR 0x4F48 53*4882a593Smuzhiyun #define BXTWC_THRMZN2L_ADDR 0x4F49 54*4882a593Smuzhiyun #define BXTWC_THRMZN3H_ADDR 0x4F4A 55*4882a593Smuzhiyun #define BXTWC_THRMZN3L_ADDR 0x4F4B 56*4882a593Smuzhiyun #define BXTWC_THRMZN4H_ADDR 0x4F4C 57*4882a593Smuzhiyun #define BXTWC_THRMZN4L_ADDR 0x4F4D 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #endif 60