1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun #ifndef MFD_INTEL_PMC_BXT_H
3*4882a593Smuzhiyun #define MFD_INTEL_PMC_BXT_H
4*4882a593Smuzhiyun
5*4882a593Smuzhiyun /* GCR reg offsets from GCR base */
6*4882a593Smuzhiyun #define PMC_GCR_PMC_CFG_REG 0x08
7*4882a593Smuzhiyun #define PMC_GCR_TELEM_DEEP_S0IX_REG 0x78
8*4882a593Smuzhiyun #define PMC_GCR_TELEM_SHLW_S0IX_REG 0x80
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun /* PMC_CFG_REG bit masks */
11*4882a593Smuzhiyun #define PMC_CFG_NO_REBOOT_EN BIT(4)
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun /**
14*4882a593Smuzhiyun * struct intel_pmc_dev - Intel PMC device structure
15*4882a593Smuzhiyun * @dev: Pointer to the parent PMC device
16*4882a593Smuzhiyun * @scu: Pointer to the SCU IPC device data structure
17*4882a593Smuzhiyun * @gcr_mem_base: Virtual base address of GCR (Global Configuration Registers)
18*4882a593Smuzhiyun * @gcr_lock: Lock used to serialize access to GCR registers
19*4882a593Smuzhiyun * @telem_base: Pointer to telemetry SSRAM base resource or %NULL if not
20*4882a593Smuzhiyun * available
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun struct intel_pmc_dev {
23*4882a593Smuzhiyun struct device *dev;
24*4882a593Smuzhiyun struct intel_scu_ipc_dev *scu;
25*4882a593Smuzhiyun void __iomem *gcr_mem_base;
26*4882a593Smuzhiyun spinlock_t gcr_lock;
27*4882a593Smuzhiyun struct resource *telem_base;
28*4882a593Smuzhiyun };
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_MFD_INTEL_PMC_BXT)
31*4882a593Smuzhiyun int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset, u64 *data);
32*4882a593Smuzhiyun int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset, u32 mask, u32 val);
33*4882a593Smuzhiyun int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data);
34*4882a593Smuzhiyun #else
intel_pmc_gcr_read64(struct intel_pmc_dev * pmc,u32 offset,u64 * data)35*4882a593Smuzhiyun static inline int intel_pmc_gcr_read64(struct intel_pmc_dev *pmc, u32 offset,
36*4882a593Smuzhiyun u64 *data)
37*4882a593Smuzhiyun {
38*4882a593Smuzhiyun return -ENOTSUPP;
39*4882a593Smuzhiyun }
40*4882a593Smuzhiyun
intel_pmc_gcr_update(struct intel_pmc_dev * pmc,u32 offset,u32 mask,u32 val)41*4882a593Smuzhiyun static inline int intel_pmc_gcr_update(struct intel_pmc_dev *pmc, u32 offset,
42*4882a593Smuzhiyun u32 mask, u32 val)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun return -ENOTSUPP;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun
intel_pmc_s0ix_counter_read(struct intel_pmc_dev * pmc,u64 * data)47*4882a593Smuzhiyun static inline int intel_pmc_s0ix_counter_read(struct intel_pmc_dev *pmc, u64 *data)
48*4882a593Smuzhiyun {
49*4882a593Smuzhiyun return -ENOTSUPP;
50*4882a593Smuzhiyun }
51*4882a593Smuzhiyun #endif
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun #endif /* MFD_INTEL_PMC_BXT_H */
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