1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Intel MAX 10 Board Management Controller chip.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2018-2020 Intel Corporation, Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #ifndef __MFD_INTEL_M10_BMC_H
8*4882a593Smuzhiyun #define __MFD_INTEL_M10_BMC_H
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #include <linux/regmap.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #define M10BMC_LEGACY_SYS_BASE 0x300400
13*4882a593Smuzhiyun #define M10BMC_SYS_BASE 0x300800
14*4882a593Smuzhiyun #define M10BMC_MEM_END 0x1fffffff
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun /* Register offset of system registers */
17*4882a593Smuzhiyun #define NIOS2_FW_VERSION 0x0
18*4882a593Smuzhiyun #define M10BMC_TEST_REG 0x3c
19*4882a593Smuzhiyun #define M10BMC_BUILD_VER 0x68
20*4882a593Smuzhiyun #define M10BMC_VER_MAJOR_MSK GENMASK(23, 16)
21*4882a593Smuzhiyun #define M10BMC_VER_PCB_INFO_MSK GENMASK(31, 24)
22*4882a593Smuzhiyun #define M10BMC_VER_LEGACY_INVALID 0xffffffff
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun /**
25*4882a593Smuzhiyun * struct intel_m10bmc - Intel MAX 10 BMC parent driver data structure
26*4882a593Smuzhiyun * @dev: this device
27*4882a593Smuzhiyun * @regmap: the regmap used to access registers by m10bmc itself
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun struct intel_m10bmc {
30*4882a593Smuzhiyun struct device *dev;
31*4882a593Smuzhiyun struct regmap *regmap;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /*
35*4882a593Smuzhiyun * register access helper functions.
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * m10bmc_raw_read - read m10bmc register per addr
38*4882a593Smuzhiyun * m10bmc_sys_read - read m10bmc system register per offset
39*4882a593Smuzhiyun */
40*4882a593Smuzhiyun static inline int
m10bmc_raw_read(struct intel_m10bmc * m10bmc,unsigned int addr,unsigned int * val)41*4882a593Smuzhiyun m10bmc_raw_read(struct intel_m10bmc *m10bmc, unsigned int addr,
42*4882a593Smuzhiyun unsigned int *val)
43*4882a593Smuzhiyun {
44*4882a593Smuzhiyun int ret;
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun ret = regmap_read(m10bmc->regmap, addr, val);
47*4882a593Smuzhiyun if (ret)
48*4882a593Smuzhiyun dev_err(m10bmc->dev, "fail to read raw reg %x: %d\n",
49*4882a593Smuzhiyun addr, ret);
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun return ret;
52*4882a593Smuzhiyun }
53*4882a593Smuzhiyun
54*4882a593Smuzhiyun /*
55*4882a593Smuzhiyun * The base of the system registers could be configured by HW developers, and
56*4882a593Smuzhiyun * in HW SPEC, the base is not added to the addresses of the system registers.
57*4882a593Smuzhiyun *
58*4882a593Smuzhiyun * This macro helps to simplify the accessing of the system registers. And if
59*4882a593Smuzhiyun * the base is reconfigured in HW, SW developers could simply change the
60*4882a593Smuzhiyun * M10BMC_SYS_BASE accordingly.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun #define m10bmc_sys_read(m10bmc, offset, val) \
63*4882a593Smuzhiyun m10bmc_raw_read(m10bmc, M10BMC_SYS_BASE + (offset), val)
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun #endif /* __MFD_INTEL_M10_BMC_H */
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