1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header file for the Ingenic JZ47xx TCU driver 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __LINUX_MFD_INGENIC_TCU_H_ 6*4882a593Smuzhiyun #define __LINUX_MFD_INGENIC_TCU_H_ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/bitops.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #define TCU_REG_WDT_TDR 0x00 11*4882a593Smuzhiyun #define TCU_REG_WDT_TCER 0x04 12*4882a593Smuzhiyun #define TCU_REG_WDT_TCNT 0x08 13*4882a593Smuzhiyun #define TCU_REG_WDT_TCSR 0x0c 14*4882a593Smuzhiyun #define TCU_REG_TER 0x10 15*4882a593Smuzhiyun #define TCU_REG_TESR 0x14 16*4882a593Smuzhiyun #define TCU_REG_TECR 0x18 17*4882a593Smuzhiyun #define TCU_REG_TSR 0x1c 18*4882a593Smuzhiyun #define TCU_REG_TFR 0x20 19*4882a593Smuzhiyun #define TCU_REG_TFSR 0x24 20*4882a593Smuzhiyun #define TCU_REG_TFCR 0x28 21*4882a593Smuzhiyun #define TCU_REG_TSSR 0x2c 22*4882a593Smuzhiyun #define TCU_REG_TMR 0x30 23*4882a593Smuzhiyun #define TCU_REG_TMSR 0x34 24*4882a593Smuzhiyun #define TCU_REG_TMCR 0x38 25*4882a593Smuzhiyun #define TCU_REG_TSCR 0x3c 26*4882a593Smuzhiyun #define TCU_REG_TDFR0 0x40 27*4882a593Smuzhiyun #define TCU_REG_TDHR0 0x44 28*4882a593Smuzhiyun #define TCU_REG_TCNT0 0x48 29*4882a593Smuzhiyun #define TCU_REG_TCSR0 0x4c 30*4882a593Smuzhiyun #define TCU_REG_OST_DR 0xe0 31*4882a593Smuzhiyun #define TCU_REG_OST_CNTL 0xe4 32*4882a593Smuzhiyun #define TCU_REG_OST_CNTH 0xe8 33*4882a593Smuzhiyun #define TCU_REG_OST_TCSR 0xec 34*4882a593Smuzhiyun #define TCU_REG_TSTR 0xf0 35*4882a593Smuzhiyun #define TCU_REG_TSTSR 0xf4 36*4882a593Smuzhiyun #define TCU_REG_TSTCR 0xf8 37*4882a593Smuzhiyun #define TCU_REG_OST_CNTHBUF 0xfc 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define TCU_TCSR_RESERVED_BITS 0x3f 40*4882a593Smuzhiyun #define TCU_TCSR_PARENT_CLOCK_MASK 0x07 41*4882a593Smuzhiyun #define TCU_TCSR_PRESCALE_LSB 3 42*4882a593Smuzhiyun #define TCU_TCSR_PRESCALE_MASK 0x38 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define TCU_TCSR_PWM_SD BIT(9) /* 0: Shutdown gracefully 1: abruptly */ 45*4882a593Smuzhiyun #define TCU_TCSR_PWM_INITL_HIGH BIT(8) /* Sets the initial output level */ 46*4882a593Smuzhiyun #define TCU_TCSR_PWM_EN BIT(7) /* PWM pin output enable */ 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define TCU_WDT_TCER_TCEN BIT(0) /* Watchdog timer enable */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define TCU_CHANNEL_STRIDE 0x10 51*4882a593Smuzhiyun #define TCU_REG_TDFRc(c) (TCU_REG_TDFR0 + ((c) * TCU_CHANNEL_STRIDE)) 52*4882a593Smuzhiyun #define TCU_REG_TDHRc(c) (TCU_REG_TDHR0 + ((c) * TCU_CHANNEL_STRIDE)) 53*4882a593Smuzhiyun #define TCU_REG_TCNTc(c) (TCU_REG_TCNT0 + ((c) * TCU_CHANNEL_STRIDE)) 54*4882a593Smuzhiyun #define TCU_REG_TCSRc(c) (TCU_REG_TCSR0 + ((c) * TCU_CHANNEL_STRIDE)) 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #endif /* __LINUX_MFD_INGENIC_TCU_H_ */ 57