1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Device driver for regulators in hi655x IC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) 2016 Hisilicon. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Authors: 8*4882a593Smuzhiyun * Chen Feng <puck.chen@hisilicon.com> 9*4882a593Smuzhiyun * Fei Wang <w.f@huawei.com> 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef __HI655X_PMIC_H 13*4882a593Smuzhiyun #define __HI655X_PMIC_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* Hi655x registers are mapped to memory bus in 4 bytes stride */ 16*4882a593Smuzhiyun #define HI655X_STRIDE 4 17*4882a593Smuzhiyun #define HI655X_BUS_ADDR(x) ((x) << 2) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define HI655X_BITS 8 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define HI655X_NR_IRQ 32 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define HI655X_IRQ_STAT_BASE (0x003 << 2) 24*4882a593Smuzhiyun #define HI655X_IRQ_MASK_BASE (0x007 << 2) 25*4882a593Smuzhiyun #define HI655X_ANA_IRQM_BASE (0x1b5 << 2) 26*4882a593Smuzhiyun #define HI655X_IRQ_ARRAY 4 27*4882a593Smuzhiyun #define HI655X_IRQ_MASK 0xFF 28*4882a593Smuzhiyun #define HI655X_IRQ_CLR 0xFF 29*4882a593Smuzhiyun #define HI655X_VER_REG 0x00 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define PMU_VER_START 0x10 32*4882a593Smuzhiyun #define PMU_VER_END 0x38 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define RESERVE_INT 7 35*4882a593Smuzhiyun #define PWRON_D20R_INT 6 36*4882a593Smuzhiyun #define PWRON_D20F_INT 5 37*4882a593Smuzhiyun #define PWRON_D4SR_INT 4 38*4882a593Smuzhiyun #define VSYS_6P0_D200UR_INT 3 39*4882a593Smuzhiyun #define VSYS_UV_D3R_INT 2 40*4882a593Smuzhiyun #define VSYS_2P5_R_INT 1 41*4882a593Smuzhiyun #define OTMP_D1R_INT 0 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define RESERVE_INT_MASK BIT(RESERVE_INT) 44*4882a593Smuzhiyun #define PWRON_D20R_INT_MASK BIT(PWRON_D20R_INT) 45*4882a593Smuzhiyun #define PWRON_D20F_INT_MASK BIT(PWRON_D20F_INT) 46*4882a593Smuzhiyun #define PWRON_D4SR_INT_MASK BIT(PWRON_D4SR_INT) 47*4882a593Smuzhiyun #define VSYS_6P0_D200UR_INT_MASK BIT(VSYS_6P0_D200UR_INT) 48*4882a593Smuzhiyun #define VSYS_UV_D3R_INT_MASK BIT(VSYS_UV_D3R_INT) 49*4882a593Smuzhiyun #define VSYS_2P5_R_INT_MASK BIT(VSYS_2P5_R_INT) 50*4882a593Smuzhiyun #define OTMP_D1R_INT_MASK BIT(OTMP_D1R_INT) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct hi655x_pmic { 53*4882a593Smuzhiyun struct resource *res; 54*4882a593Smuzhiyun struct device *dev; 55*4882a593Smuzhiyun struct regmap *regmap; 56*4882a593Smuzhiyun int gpio; 57*4882a593Smuzhiyun unsigned int ver; 58*4882a593Smuzhiyun struct regmap_irq_chip_data *irq_data; 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #endif 62