1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Header file for device driver Hi6421 PMIC 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (c) <2011-2014> HiSilicon Technologies Co., Ltd. 6*4882a593Smuzhiyun * http://www.hisilicon.com 7*4882a593Smuzhiyun * Copyright (c) <2013-2014> Linaro Ltd. 8*4882a593Smuzhiyun * https://www.linaro.org 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * Author: Guodong Xu <guodong.xu@linaro.org> 11*4882a593Smuzhiyun */ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #ifndef __HI6421_PMIC_H 14*4882a593Smuzhiyun #define __HI6421_PMIC_H 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Hi6421 registers are mapped to memory bus in 4 bytes stride */ 17*4882a593Smuzhiyun #define HI6421_REG_TO_BUS_ADDR(x) (x << 2) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Hi6421 maximum register number */ 20*4882a593Smuzhiyun #define HI6421_REG_MAX 0xFF 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Hi6421 OCP (over current protection) and DEB (debounce) control register */ 23*4882a593Smuzhiyun #define HI6421_OCP_DEB_CTRL_REG HI6421_REG_TO_BUS_ADDR(0x51) 24*4882a593Smuzhiyun #define HI6421_OCP_DEB_SEL_MASK 0x0C 25*4882a593Smuzhiyun #define HI6421_OCP_DEB_SEL_8MS 0x00 26*4882a593Smuzhiyun #define HI6421_OCP_DEB_SEL_16MS 0x04 27*4882a593Smuzhiyun #define HI6421_OCP_DEB_SEL_32MS 0x08 28*4882a593Smuzhiyun #define HI6421_OCP_DEB_SEL_64MS 0x0C 29*4882a593Smuzhiyun #define HI6421_OCP_EN_DEBOUNCE_MASK 0x02 30*4882a593Smuzhiyun #define HI6421_OCP_EN_DEBOUNCE_ENABLE 0x02 31*4882a593Smuzhiyun #define HI6421_OCP_AUTO_STOP_MASK 0x01 32*4882a593Smuzhiyun #define HI6421_OCP_AUTO_STOP_ENABLE 0x01 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun struct hi6421_pmic { 35*4882a593Smuzhiyun struct regmap *regmap; 36*4882a593Smuzhiyun }; 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun enum hi6421_type { 39*4882a593Smuzhiyun HI6421 = 0, 40*4882a593Smuzhiyun HI6421_V530, 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #endif /* __HI6421_PMIC_H */ 44