1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun * 3*4882a593Smuzhiyun * Copyright (C) 2020 Gateworks Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef __LINUX_MFD_GSC_H_ 6*4882a593Smuzhiyun #define __LINUX_MFD_GSC_H_ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <linux/regmap.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun /* Device Addresses */ 11*4882a593Smuzhiyun #define GSC_MISC 0x20 12*4882a593Smuzhiyun #define GSC_UPDATE 0x21 13*4882a593Smuzhiyun #define GSC_GPIO 0x23 14*4882a593Smuzhiyun #define GSC_HWMON 0x29 15*4882a593Smuzhiyun #define GSC_EEPROM0 0x50 16*4882a593Smuzhiyun #define GSC_EEPROM1 0x51 17*4882a593Smuzhiyun #define GSC_EEPROM2 0x52 18*4882a593Smuzhiyun #define GSC_EEPROM3 0x53 19*4882a593Smuzhiyun #define GSC_RTC 0x68 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* Register offsets */ 22*4882a593Smuzhiyun enum { 23*4882a593Smuzhiyun GSC_CTRL_0 = 0x00, 24*4882a593Smuzhiyun GSC_CTRL_1 = 0x01, 25*4882a593Smuzhiyun GSC_TIME = 0x02, 26*4882a593Smuzhiyun GSC_TIME_ADD = 0x06, 27*4882a593Smuzhiyun GSC_IRQ_STATUS = 0x0A, 28*4882a593Smuzhiyun GSC_IRQ_ENABLE = 0x0B, 29*4882a593Smuzhiyun GSC_FW_CRC = 0x0C, 30*4882a593Smuzhiyun GSC_FW_VER = 0x0E, 31*4882a593Smuzhiyun GSC_WP = 0x0F, 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Bit definitions */ 35*4882a593Smuzhiyun #define GSC_CTRL_0_PB_HARD_RESET 0 36*4882a593Smuzhiyun #define GSC_CTRL_0_PB_CLEAR_SECURE_KEY 1 37*4882a593Smuzhiyun #define GSC_CTRL_0_PB_SOFT_POWER_DOWN 2 38*4882a593Smuzhiyun #define GSC_CTRL_0_PB_BOOT_ALTERNATE 3 39*4882a593Smuzhiyun #define GSC_CTRL_0_PERFORM_CRC 4 40*4882a593Smuzhiyun #define GSC_CTRL_0_TAMPER_DETECT 5 41*4882a593Smuzhiyun #define GSC_CTRL_0_SWITCH_HOLD 6 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define GSC_CTRL_1_SLEEP_ENABLE 0 44*4882a593Smuzhiyun #define GSC_CTRL_1_SLEEP_ACTIVATE 1 45*4882a593Smuzhiyun #define GSC_CTRL_1_SLEEP_ADD 2 46*4882a593Smuzhiyun #define GSC_CTRL_1_SLEEP_NOWAKEPB 3 47*4882a593Smuzhiyun #define GSC_CTRL_1_WDT_TIME 4 48*4882a593Smuzhiyun #define GSC_CTRL_1_WDT_ENABLE 5 49*4882a593Smuzhiyun #define GSC_CTRL_1_SWITCH_BOOT_ENABLE 6 50*4882a593Smuzhiyun #define GSC_CTRL_1_SWITCH_BOOT_CLEAR 7 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define GSC_IRQ_PB 0 53*4882a593Smuzhiyun #define GSC_IRQ_KEY_ERASED 1 54*4882a593Smuzhiyun #define GSC_IRQ_EEPROM_WP 2 55*4882a593Smuzhiyun #define GSC_IRQ_RESV 3 56*4882a593Smuzhiyun #define GSC_IRQ_GPIO 4 57*4882a593Smuzhiyun #define GSC_IRQ_TAMPER 5 58*4882a593Smuzhiyun #define GSC_IRQ_WDT_TIMEOUT 6 59*4882a593Smuzhiyun #define GSC_IRQ_SWITCH_HOLD 7 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun int gsc_read(void *context, unsigned int reg, unsigned int *val); 62*4882a593Smuzhiyun int gsc_write(void *context, unsigned int reg, unsigned int val); 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun struct gsc_dev { 65*4882a593Smuzhiyun struct device *dev; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct i2c_client *i2c; /* 0x20: interrupt controller, WDT */ 68*4882a593Smuzhiyun struct i2c_client *i2c_hwmon; /* 0x29: hwmon, fan controller */ 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct regmap *regmap; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun unsigned int fwver; 73*4882a593Smuzhiyun unsigned short fwcrc; 74*4882a593Smuzhiyun }; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #endif /* __LINUX_MFD_GSC_H_ */ 77