1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* MFD cell driver data for the DS1WM driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * to be defined in the MFD device that is 5*4882a593Smuzhiyun * using this driver for one of his sub devices 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun struct ds1wm_driver_data { 9*4882a593Smuzhiyun int active_high; 10*4882a593Smuzhiyun int clock_rate; 11*4882a593Smuzhiyun /* in milliseconds, the amount of time to 12*4882a593Smuzhiyun * sleep following a reset pulse. Zero 13*4882a593Smuzhiyun * should work if your bus devices recover 14*4882a593Smuzhiyun * time respects the 1-wire spec since the 15*4882a593Smuzhiyun * ds1wm implements the precise timings of 16*4882a593Smuzhiyun * a reset pulse/presence detect sequence. 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun unsigned int reset_recover_delay; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Say 1 here for big endian Hardware 21*4882a593Smuzhiyun * (only relevant with bus-shift > 0 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun bool is_hw_big_endian; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* left shift of register number to get register address offsett. 26*4882a593Smuzhiyun * Only 0,1,2 allowed for 8,16 or 32 bit bus width respectively 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun unsigned int bus_shift; 29*4882a593Smuzhiyun }; 30