1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * dm355evm_msp.h - support MSP430 microcontroller on DM355EVM board 3*4882a593Smuzhiyun */ 4*4882a593Smuzhiyun #ifndef __LINUX_I2C_DM355EVM_MSP 5*4882a593Smuzhiyun #define __LINUX_I2C_DM355EVM_MSP 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* 8*4882a593Smuzhiyun * Written against Spectrum's writeup for the A4 firmware revision, 9*4882a593Smuzhiyun * and tweaked to match source and rev D2 schematics by removing CPLD 10*4882a593Smuzhiyun * and NOR flash hooks (which were last appropriate in rev B boards). 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Note that the firmware supports a flavor of write posting ... to be 13*4882a593Smuzhiyun * sure a write completes, issue another read or write. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* utilities to access "registers" emulated by msp430 firmware */ 17*4882a593Smuzhiyun extern int dm355evm_msp_write(u8 value, u8 reg); 18*4882a593Smuzhiyun extern int dm355evm_msp_read(u8 reg); 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun /* command/control registers */ 22*4882a593Smuzhiyun #define DM355EVM_MSP_COMMAND 0x00 23*4882a593Smuzhiyun # define MSP_COMMAND_NULL 0 24*4882a593Smuzhiyun # define MSP_COMMAND_RESET_COLD 1 25*4882a593Smuzhiyun # define MSP_COMMAND_RESET_WARM 2 26*4882a593Smuzhiyun # define MSP_COMMAND_RESET_WARM_I 3 27*4882a593Smuzhiyun # define MSP_COMMAND_POWEROFF 4 28*4882a593Smuzhiyun # define MSP_COMMAND_IR_REINIT 5 29*4882a593Smuzhiyun #define DM355EVM_MSP_STATUS 0x01 30*4882a593Smuzhiyun # define MSP_STATUS_BAD_OFFSET BIT(0) 31*4882a593Smuzhiyun # define MSP_STATUS_BAD_COMMAND BIT(1) 32*4882a593Smuzhiyun # define MSP_STATUS_POWER_ERROR BIT(2) 33*4882a593Smuzhiyun # define MSP_STATUS_RXBUF_OVERRUN BIT(3) 34*4882a593Smuzhiyun #define DM355EVM_MSP_RESET 0x02 /* 0 bits == in reset */ 35*4882a593Smuzhiyun # define MSP_RESET_DC5 BIT(0) 36*4882a593Smuzhiyun # define MSP_RESET_TVP5154 BIT(2) 37*4882a593Smuzhiyun # define MSP_RESET_IMAGER BIT(3) 38*4882a593Smuzhiyun # define MSP_RESET_ETHERNET BIT(4) 39*4882a593Smuzhiyun # define MSP_RESET_SYS BIT(5) 40*4882a593Smuzhiyun # define MSP_RESET_AIC33 BIT(7) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* GPIO registers ... bit patterns mostly match the source MSP ports */ 43*4882a593Smuzhiyun #define DM355EVM_MSP_LED 0x03 /* active low (MSP P4) */ 44*4882a593Smuzhiyun #define DM355EVM_MSP_SWITCH1 0x04 /* (MSP P5, masked) */ 45*4882a593Smuzhiyun # define MSP_SWITCH1_SW6_1 BIT(0) 46*4882a593Smuzhiyun # define MSP_SWITCH1_SW6_2 BIT(1) 47*4882a593Smuzhiyun # define MSP_SWITCH1_SW6_3 BIT(2) 48*4882a593Smuzhiyun # define MSP_SWITCH1_SW6_4 BIT(3) 49*4882a593Smuzhiyun # define MSP_SWITCH1_J1 BIT(4) /* NTSC/PAL */ 50*4882a593Smuzhiyun # define MSP_SWITCH1_MSP_INT BIT(5) /* active low */ 51*4882a593Smuzhiyun #define DM355EVM_MSP_SWITCH2 0x05 /* (MSP P6, masked) */ 52*4882a593Smuzhiyun # define MSP_SWITCH2_SW10 BIT(3) 53*4882a593Smuzhiyun # define MSP_SWITCH2_SW11 BIT(4) 54*4882a593Smuzhiyun # define MSP_SWITCH2_SW12 BIT(5) 55*4882a593Smuzhiyun # define MSP_SWITCH2_SW13 BIT(6) 56*4882a593Smuzhiyun # define MSP_SWITCH2_SW14 BIT(7) 57*4882a593Smuzhiyun #define DM355EVM_MSP_SDMMC 0x06 /* (MSP P2, masked) */ 58*4882a593Smuzhiyun # define MSP_SDMMC_0_WP BIT(1) 59*4882a593Smuzhiyun # define MSP_SDMMC_0_CD BIT(2) /* active low */ 60*4882a593Smuzhiyun # define MSP_SDMMC_1_WP BIT(3) 61*4882a593Smuzhiyun # define MSP_SDMMC_1_CD BIT(4) /* active low */ 62*4882a593Smuzhiyun #define DM355EVM_MSP_FIRMREV 0x07 /* not a GPIO (out of order) */ 63*4882a593Smuzhiyun #define DM355EVM_MSP_VIDEO_IN 0x08 /* (MSP P3, masked) */ 64*4882a593Smuzhiyun # define MSP_VIDEO_IMAGER BIT(7) /* low == tvp5146 */ 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* power supply registers are currently omitted */ 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* RTC registers */ 69*4882a593Smuzhiyun #define DM355EVM_MSP_RTC_0 0x12 /* LSB */ 70*4882a593Smuzhiyun #define DM355EVM_MSP_RTC_1 0x13 71*4882a593Smuzhiyun #define DM355EVM_MSP_RTC_2 0x14 72*4882a593Smuzhiyun #define DM355EVM_MSP_RTC_3 0x15 /* MSB */ 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* input event queue registers; code == ((HIGH << 8) | LOW) */ 75*4882a593Smuzhiyun #define DM355EVM_MSP_INPUT_COUNT 0x16 /* decrement by reading LOW */ 76*4882a593Smuzhiyun #define DM355EVM_MSP_INPUT_HIGH 0x17 77*4882a593Smuzhiyun #define DM355EVM_MSP_INPUT_LOW 0x18 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun #endif /* __LINUX_I2C_DM355EVM_MSP */ 80