1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * DaVinci Voice Codec Core Interface for TI platforms 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2010 Texas Instruments, Inc 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_ 11*4882a593Smuzhiyun #define __LINUX_MFD_DAVINCI_VOICECODEC_H_ 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/kernel.h> 14*4882a593Smuzhiyun #include <linux/platform_device.h> 15*4882a593Smuzhiyun #include <linux/mfd/core.h> 16*4882a593Smuzhiyun #include <linux/platform_data/edma.h> 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun struct regmap; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * Register values. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #define DAVINCI_VC_PID 0x00 24*4882a593Smuzhiyun #define DAVINCI_VC_CTRL 0x04 25*4882a593Smuzhiyun #define DAVINCI_VC_INTEN 0x08 26*4882a593Smuzhiyun #define DAVINCI_VC_INTSTATUS 0x0c 27*4882a593Smuzhiyun #define DAVINCI_VC_INTCLR 0x10 28*4882a593Smuzhiyun #define DAVINCI_VC_EMUL_CTRL 0x14 29*4882a593Smuzhiyun #define DAVINCI_VC_RFIFO 0x20 30*4882a593Smuzhiyun #define DAVINCI_VC_WFIFO 0x24 31*4882a593Smuzhiyun #define DAVINCI_VC_FIFOSTAT 0x28 32*4882a593Smuzhiyun #define DAVINCI_VC_TST_CTRL 0x2C 33*4882a593Smuzhiyun #define DAVINCI_VC_REG05 0x94 34*4882a593Smuzhiyun #define DAVINCI_VC_REG09 0xA4 35*4882a593Smuzhiyun #define DAVINCI_VC_REG12 0xB0 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun /* DAVINCI_VC_CTRL bit fields */ 38*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_MASK 0x5500 39*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_RSTADC BIT(0) 40*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_RSTDAC BIT(1) 41*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4) 42*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5) 43*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6) 44*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7) 45*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_RFIFOEN BIT(8) 46*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_RFIFOCL BIT(9) 47*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10) 48*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_WFIFOEN BIT(12) 49*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_WFIFOCL BIT(13) 50*4882a593Smuzhiyun #define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14) 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun /* DAVINCI_VC_INT bit fields */ 53*4882a593Smuzhiyun #define DAVINCI_VC_INT_MASK 0x3F 54*4882a593Smuzhiyun #define DAVINCI_VC_INT_RDRDY_MASK BIT(0) 55*4882a593Smuzhiyun #define DAVINCI_VC_INT_RERROVF_MASK BIT(1) 56*4882a593Smuzhiyun #define DAVINCI_VC_INT_RERRUDR_MASK BIT(2) 57*4882a593Smuzhiyun #define DAVINCI_VC_INT_WDREQ_MASK BIT(3) 58*4882a593Smuzhiyun #define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4) 59*4882a593Smuzhiyun #define DAVINCI_VC_INT_WERRUDR_MASK BIT(5) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* DAVINCI_VC_REG05 bit fields */ 62*4882a593Smuzhiyun #define DAVINCI_VC_REG05_PGA_GAIN 0x07 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* DAVINCI_VC_REG09 bit fields */ 65*4882a593Smuzhiyun #define DAVINCI_VC_REG09_MUTE 0x40 66*4882a593Smuzhiyun #define DAVINCI_VC_REG09_DIG_ATTEN 0x3F 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun /* DAVINCI_VC_REG12 bit fields */ 69*4882a593Smuzhiyun #define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD 70*4882a593Smuzhiyun #define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define DAVINCI_VC_CELLS 2 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun enum davinci_vc_cells { 75*4882a593Smuzhiyun DAVINCI_VC_VCIF_CELL, 76*4882a593Smuzhiyun DAVINCI_VC_CQ93VC_CELL, 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct davinci_vcif { 80*4882a593Smuzhiyun struct platform_device *pdev; 81*4882a593Smuzhiyun u32 dma_tx_channel; 82*4882a593Smuzhiyun u32 dma_rx_channel; 83*4882a593Smuzhiyun dma_addr_t dma_tx_addr; 84*4882a593Smuzhiyun dma_addr_t dma_rx_addr; 85*4882a593Smuzhiyun }; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun struct davinci_vc { 88*4882a593Smuzhiyun /* Device data */ 89*4882a593Smuzhiyun struct device *dev; 90*4882a593Smuzhiyun struct platform_device *pdev; 91*4882a593Smuzhiyun struct clk *clk; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun /* Memory resources */ 94*4882a593Smuzhiyun void __iomem *base; 95*4882a593Smuzhiyun struct regmap *regmap; 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun /* MFD cells */ 98*4882a593Smuzhiyun struct mfd_cell cells[DAVINCI_VC_CELLS]; 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* Client devices */ 101*4882a593Smuzhiyun struct davinci_vcif davinci_vcif; 102*4882a593Smuzhiyun }; 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun #endif 105