1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * da9052 declarations for DA9052 PMICs.
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright(c) 2011 Dialog Semiconductor Ltd.
6*4882a593Smuzhiyun *
7*4882a593Smuzhiyun * Author: David Dajun Chen <dchen@diasemi.com>
8*4882a593Smuzhiyun */
9*4882a593Smuzhiyun
10*4882a593Smuzhiyun #ifndef __MFD_DA9052_DA9052_H
11*4882a593Smuzhiyun #define __MFD_DA9052_DA9052_H
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #include <linux/interrupt.h>
14*4882a593Smuzhiyun #include <linux/regmap.h>
15*4882a593Smuzhiyun #include <linux/slab.h>
16*4882a593Smuzhiyun #include <linux/completion.h>
17*4882a593Smuzhiyun #include <linux/list.h>
18*4882a593Smuzhiyun #include <linux/mfd/core.h>
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/mfd/da9052/reg.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* Common - HWMON Channel Definations */
23*4882a593Smuzhiyun #define DA9052_ADC_VDDOUT 0
24*4882a593Smuzhiyun #define DA9052_ADC_ICH 1
25*4882a593Smuzhiyun #define DA9052_ADC_TBAT 2
26*4882a593Smuzhiyun #define DA9052_ADC_VBAT 3
27*4882a593Smuzhiyun #define DA9052_ADC_IN4 4
28*4882a593Smuzhiyun #define DA9052_ADC_IN5 5
29*4882a593Smuzhiyun #define DA9052_ADC_IN6 6
30*4882a593Smuzhiyun #define DA9052_ADC_TSI 7
31*4882a593Smuzhiyun #define DA9052_ADC_TJUNC 8
32*4882a593Smuzhiyun #define DA9052_ADC_VBBAT 9
33*4882a593Smuzhiyun
34*4882a593Smuzhiyun /* TSI channel has its own 4 channel mux */
35*4882a593Smuzhiyun #define DA9052_ADC_TSI_XP 70
36*4882a593Smuzhiyun #define DA9052_ADC_TSI_XN 71
37*4882a593Smuzhiyun #define DA9052_ADC_TSI_YP 72
38*4882a593Smuzhiyun #define DA9052_ADC_TSI_YN 73
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun #define DA9052_IRQ_DCIN 0
41*4882a593Smuzhiyun #define DA9052_IRQ_VBUS 1
42*4882a593Smuzhiyun #define DA9052_IRQ_DCINREM 2
43*4882a593Smuzhiyun #define DA9052_IRQ_VBUSREM 3
44*4882a593Smuzhiyun #define DA9052_IRQ_VDDLOW 4
45*4882a593Smuzhiyun #define DA9052_IRQ_ALARM 5
46*4882a593Smuzhiyun #define DA9052_IRQ_SEQRDY 6
47*4882a593Smuzhiyun #define DA9052_IRQ_COMP1V2 7
48*4882a593Smuzhiyun #define DA9052_IRQ_NONKEY 8
49*4882a593Smuzhiyun #define DA9052_IRQ_IDFLOAT 9
50*4882a593Smuzhiyun #define DA9052_IRQ_IDGND 10
51*4882a593Smuzhiyun #define DA9052_IRQ_CHGEND 11
52*4882a593Smuzhiyun #define DA9052_IRQ_TBAT 12
53*4882a593Smuzhiyun #define DA9052_IRQ_ADC_EOM 13
54*4882a593Smuzhiyun #define DA9052_IRQ_PENDOWN 14
55*4882a593Smuzhiyun #define DA9052_IRQ_TSIREADY 15
56*4882a593Smuzhiyun #define DA9052_IRQ_GPI0 16
57*4882a593Smuzhiyun #define DA9052_IRQ_GPI1 17
58*4882a593Smuzhiyun #define DA9052_IRQ_GPI2 18
59*4882a593Smuzhiyun #define DA9052_IRQ_GPI3 19
60*4882a593Smuzhiyun #define DA9052_IRQ_GPI4 20
61*4882a593Smuzhiyun #define DA9052_IRQ_GPI5 21
62*4882a593Smuzhiyun #define DA9052_IRQ_GPI6 22
63*4882a593Smuzhiyun #define DA9052_IRQ_GPI7 23
64*4882a593Smuzhiyun #define DA9052_IRQ_GPI8 24
65*4882a593Smuzhiyun #define DA9052_IRQ_GPI9 25
66*4882a593Smuzhiyun #define DA9052_IRQ_GPI10 26
67*4882a593Smuzhiyun #define DA9052_IRQ_GPI11 27
68*4882a593Smuzhiyun #define DA9052_IRQ_GPI12 28
69*4882a593Smuzhiyun #define DA9052_IRQ_GPI13 29
70*4882a593Smuzhiyun #define DA9052_IRQ_GPI14 30
71*4882a593Smuzhiyun #define DA9052_IRQ_GPI15 31
72*4882a593Smuzhiyun
73*4882a593Smuzhiyun enum da9052_chip_id {
74*4882a593Smuzhiyun DA9052,
75*4882a593Smuzhiyun DA9053_AA,
76*4882a593Smuzhiyun DA9053_BA,
77*4882a593Smuzhiyun DA9053_BB,
78*4882a593Smuzhiyun DA9053_BC,
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct da9052_pdata;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun struct da9052 {
84*4882a593Smuzhiyun struct device *dev;
85*4882a593Smuzhiyun struct regmap *regmap;
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun struct mutex auxadc_lock;
88*4882a593Smuzhiyun struct completion done;
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun int irq_base;
91*4882a593Smuzhiyun struct regmap_irq_chip_data *irq_data;
92*4882a593Smuzhiyun u8 chip_id;
93*4882a593Smuzhiyun
94*4882a593Smuzhiyun int chip_irq;
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun /* SOC I/O transfer related fixes for DA9052/53 */
97*4882a593Smuzhiyun int (*fix_io) (struct da9052 *da9052, unsigned char reg);
98*4882a593Smuzhiyun };
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun /* ADC API */
101*4882a593Smuzhiyun int da9052_adc_manual_read(struct da9052 *da9052, unsigned char channel);
102*4882a593Smuzhiyun int da9052_adc_read_temp(struct da9052 *da9052);
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* Device I/O API */
da9052_reg_read(struct da9052 * da9052,unsigned char reg)105*4882a593Smuzhiyun static inline int da9052_reg_read(struct da9052 *da9052, unsigned char reg)
106*4882a593Smuzhiyun {
107*4882a593Smuzhiyun int val, ret;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun ret = regmap_read(da9052->regmap, reg, &val);
110*4882a593Smuzhiyun if (ret < 0)
111*4882a593Smuzhiyun return ret;
112*4882a593Smuzhiyun
113*4882a593Smuzhiyun if (da9052->fix_io) {
114*4882a593Smuzhiyun ret = da9052->fix_io(da9052, reg);
115*4882a593Smuzhiyun if (ret < 0)
116*4882a593Smuzhiyun return ret;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun return val;
120*4882a593Smuzhiyun }
121*4882a593Smuzhiyun
da9052_reg_write(struct da9052 * da9052,unsigned char reg,unsigned char val)122*4882a593Smuzhiyun static inline int da9052_reg_write(struct da9052 *da9052, unsigned char reg,
123*4882a593Smuzhiyun unsigned char val)
124*4882a593Smuzhiyun {
125*4882a593Smuzhiyun int ret;
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun ret = regmap_write(da9052->regmap, reg, val);
128*4882a593Smuzhiyun if (ret < 0)
129*4882a593Smuzhiyun return ret;
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun if (da9052->fix_io) {
132*4882a593Smuzhiyun ret = da9052->fix_io(da9052, reg);
133*4882a593Smuzhiyun if (ret < 0)
134*4882a593Smuzhiyun return ret;
135*4882a593Smuzhiyun }
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun return ret;
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun
da9052_group_read(struct da9052 * da9052,unsigned char reg,unsigned reg_cnt,unsigned char * val)140*4882a593Smuzhiyun static inline int da9052_group_read(struct da9052 *da9052, unsigned char reg,
141*4882a593Smuzhiyun unsigned reg_cnt, unsigned char *val)
142*4882a593Smuzhiyun {
143*4882a593Smuzhiyun int ret;
144*4882a593Smuzhiyun unsigned int tmp;
145*4882a593Smuzhiyun int i;
146*4882a593Smuzhiyun
147*4882a593Smuzhiyun for (i = 0; i < reg_cnt; i++) {
148*4882a593Smuzhiyun ret = regmap_read(da9052->regmap, reg + i, &tmp);
149*4882a593Smuzhiyun val[i] = (unsigned char)tmp;
150*4882a593Smuzhiyun if (ret < 0)
151*4882a593Smuzhiyun return ret;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun if (da9052->fix_io) {
155*4882a593Smuzhiyun ret = da9052->fix_io(da9052, reg);
156*4882a593Smuzhiyun if (ret < 0)
157*4882a593Smuzhiyun return ret;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun return ret;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
da9052_group_write(struct da9052 * da9052,unsigned char reg,unsigned reg_cnt,unsigned char * val)163*4882a593Smuzhiyun static inline int da9052_group_write(struct da9052 *da9052, unsigned char reg,
164*4882a593Smuzhiyun unsigned reg_cnt, unsigned char *val)
165*4882a593Smuzhiyun {
166*4882a593Smuzhiyun int ret = 0;
167*4882a593Smuzhiyun int i;
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun for (i = 0; i < reg_cnt; i++) {
170*4882a593Smuzhiyun ret = regmap_write(da9052->regmap, reg + i, val[i]);
171*4882a593Smuzhiyun if (ret < 0)
172*4882a593Smuzhiyun return ret;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun if (da9052->fix_io) {
176*4882a593Smuzhiyun ret = da9052->fix_io(da9052, reg);
177*4882a593Smuzhiyun if (ret < 0)
178*4882a593Smuzhiyun return ret;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun return ret;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
da9052_reg_update(struct da9052 * da9052,unsigned char reg,unsigned char bit_mask,unsigned char reg_val)184*4882a593Smuzhiyun static inline int da9052_reg_update(struct da9052 *da9052, unsigned char reg,
185*4882a593Smuzhiyun unsigned char bit_mask,
186*4882a593Smuzhiyun unsigned char reg_val)
187*4882a593Smuzhiyun {
188*4882a593Smuzhiyun int ret;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun ret = regmap_update_bits(da9052->regmap, reg, bit_mask, reg_val);
191*4882a593Smuzhiyun if (ret < 0)
192*4882a593Smuzhiyun return ret;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun if (da9052->fix_io) {
195*4882a593Smuzhiyun ret = da9052->fix_io(da9052, reg);
196*4882a593Smuzhiyun if (ret < 0)
197*4882a593Smuzhiyun return ret;
198*4882a593Smuzhiyun }
199*4882a593Smuzhiyun
200*4882a593Smuzhiyun return ret;
201*4882a593Smuzhiyun }
202*4882a593Smuzhiyun
203*4882a593Smuzhiyun int da9052_device_init(struct da9052 *da9052, u8 chip_id);
204*4882a593Smuzhiyun void da9052_device_exit(struct da9052 *da9052);
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun extern const struct regmap_config da9052_regmap_config;
207*4882a593Smuzhiyun
208*4882a593Smuzhiyun int da9052_irq_init(struct da9052 *da9052);
209*4882a593Smuzhiyun int da9052_irq_exit(struct da9052 *da9052);
210*4882a593Smuzhiyun int da9052_request_irq(struct da9052 *da9052, int irq, char *name,
211*4882a593Smuzhiyun irq_handler_t handler, void *data);
212*4882a593Smuzhiyun void da9052_free_irq(struct da9052 *da9052, int irq, void *data);
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun int da9052_enable_irq(struct da9052 *da9052, int irq);
215*4882a593Smuzhiyun int da9052_disable_irq(struct da9052 *da9052, int irq);
216*4882a593Smuzhiyun int da9052_disable_irq_nosync(struct da9052 *da9052, int irq);
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun #endif /* __MFD_DA9052_DA9052_H */
219