1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * ROHM BD9571MWV-M driver 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (C) 2017 Marek Vasut <marek.vasut+renesas@gmail.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * This program is free software; you can redistribute it and/or 7*4882a593Smuzhiyun * modify it under the terms of the GNU General Public License version 2 as 8*4882a593Smuzhiyun * published by the Free Software Foundation. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * This program is distributed "as is" WITHOUT ANY WARRANTY of any 11*4882a593Smuzhiyun * kind, whether expressed or implied; without even the implied warranty 12*4882a593Smuzhiyun * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13*4882a593Smuzhiyun * GNU General Public License version 2 for more details. 14*4882a593Smuzhiyun * 15*4882a593Smuzhiyun * Based on the TPS65086 driver 16*4882a593Smuzhiyun */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #ifndef __LINUX_MFD_BD9571MWV_H 19*4882a593Smuzhiyun #define __LINUX_MFD_BD9571MWV_H 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #include <linux/device.h> 22*4882a593Smuzhiyun #include <linux/regmap.h> 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* List of registers for BD9571MWV */ 25*4882a593Smuzhiyun #define BD9571MWV_VENDOR_CODE 0x00 26*4882a593Smuzhiyun #define BD9571MWV_VENDOR_CODE_VAL 0xdb 27*4882a593Smuzhiyun #define BD9571MWV_PRODUCT_CODE 0x01 28*4882a593Smuzhiyun #define BD9571MWV_PRODUCT_CODE_VAL 0x60 29*4882a593Smuzhiyun #define BD9571MWV_PRODUCT_REVISION 0x02 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define BD9571MWV_I2C_FUSA_MODE 0x10 32*4882a593Smuzhiyun #define BD9571MWV_I2C_MD2_E1_BIT_1 0x11 33*4882a593Smuzhiyun #define BD9571MWV_I2C_MD2_E1_BIT_2 0x12 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define BD9571MWV_BKUP_MODE_CNT 0x20 36*4882a593Smuzhiyun #define BD9571MWV_BKUP_MODE_CNT_KEEPON_MASK GENMASK(3, 0) 37*4882a593Smuzhiyun #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0 BIT(0) 38*4882a593Smuzhiyun #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1 BIT(1) 39*4882a593Smuzhiyun #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR0C BIT(2) 40*4882a593Smuzhiyun #define BD9571MWV_BKUP_MODE_CNT_KEEPON_DDR1C BIT(3) 41*4882a593Smuzhiyun #define BD9571MWV_BKUP_MODE_STATUS 0x21 42*4882a593Smuzhiyun #define BD9571MWV_BKUP_RECOVERY_CNT 0x22 43*4882a593Smuzhiyun #define BD9571MWV_BKUP_CTRL_TIM_CNT 0x23 44*4882a593Smuzhiyun #define BD9571MWV_WAITBKUP_WDT_CNT 0x24 45*4882a593Smuzhiyun #define BD9571MWV_128H_TIM_CNT 0x26 46*4882a593Smuzhiyun #define BD9571MWV_QLLM_CNT 0x27 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun #define BD9571MWV_AVS_SET_MONI 0x31 49*4882a593Smuzhiyun #define BD9571MWV_AVS_SET_MONI_MASK 0x3 50*4882a593Smuzhiyun #define BD9571MWV_AVS_VD09_VID(n) (0x32 + (n)) 51*4882a593Smuzhiyun #define BD9571MWV_AVS_DVFS_VID(n) (0x36 + (n)) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define BD9571MWV_VD18_VID 0x42 54*4882a593Smuzhiyun #define BD9571MWV_VD25_VID 0x43 55*4882a593Smuzhiyun #define BD9571MWV_VD33_VID 0x44 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define BD9571MWV_DVFS_VINIT 0x50 58*4882a593Smuzhiyun #define BD9571MWV_DVFS_SETVMAX 0x52 59*4882a593Smuzhiyun #define BD9571MWV_DVFS_BOOSTVID 0x53 60*4882a593Smuzhiyun #define BD9571MWV_DVFS_SETVID 0x54 61*4882a593Smuzhiyun #define BD9571MWV_DVFS_MONIVDAC 0x55 62*4882a593Smuzhiyun #define BD9571MWV_DVFS_PGD_CNT 0x56 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define BD9571MWV_GPIO_DIR 0x60 65*4882a593Smuzhiyun #define BD9571MWV_GPIO_OUT 0x61 66*4882a593Smuzhiyun #define BD9571MWV_GPIO_IN 0x62 67*4882a593Smuzhiyun #define BD9571MWV_GPIO_DEB 0x63 68*4882a593Smuzhiyun #define BD9571MWV_GPIO_INT_SET 0x64 69*4882a593Smuzhiyun #define BD9571MWV_GPIO_INT 0x65 70*4882a593Smuzhiyun #define BD9571MWV_GPIO_INTMASK 0x66 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define BD9571MWV_REG_KEEP(n) (0x70 + (n)) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #define BD9571MWV_PMIC_INTERNAL_STATUS 0x80 75*4882a593Smuzhiyun #define BD9571MWV_PROT_ERROR_STATUS0 0x81 76*4882a593Smuzhiyun #define BD9571MWV_PROT_ERROR_STATUS1 0x82 77*4882a593Smuzhiyun #define BD9571MWV_PROT_ERROR_STATUS2 0x83 78*4882a593Smuzhiyun #define BD9571MWV_PROT_ERROR_STATUS3 0x84 79*4882a593Smuzhiyun #define BD9571MWV_PROT_ERROR_STATUS4 0x85 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun #define BD9571MWV_INT_INTREQ 0x90 82*4882a593Smuzhiyun #define BD9571MWV_INT_INTREQ_MD1_INT BIT(0) 83*4882a593Smuzhiyun #define BD9571MWV_INT_INTREQ_MD2_E1_INT BIT(1) 84*4882a593Smuzhiyun #define BD9571MWV_INT_INTREQ_MD2_E2_INT BIT(2) 85*4882a593Smuzhiyun #define BD9571MWV_INT_INTREQ_PROT_ERR_INT BIT(3) 86*4882a593Smuzhiyun #define BD9571MWV_INT_INTREQ_GP_INT BIT(4) 87*4882a593Smuzhiyun #define BD9571MWV_INT_INTREQ_128H_OF_INT BIT(5) 88*4882a593Smuzhiyun #define BD9571MWV_INT_INTREQ_WDT_OF_INT BIT(6) 89*4882a593Smuzhiyun #define BD9571MWV_INT_INTREQ_BKUP_TRG_INT BIT(7) 90*4882a593Smuzhiyun #define BD9571MWV_INT_INTMASK 0x91 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun #define BD9571MWV_ACCESS_KEY 0xff 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Define the BD9571MWV IRQ numbers */ 95*4882a593Smuzhiyun enum bd9571mwv_irqs { 96*4882a593Smuzhiyun BD9571MWV_IRQ_MD1, 97*4882a593Smuzhiyun BD9571MWV_IRQ_MD2_E1, 98*4882a593Smuzhiyun BD9571MWV_IRQ_MD2_E2, 99*4882a593Smuzhiyun BD9571MWV_IRQ_PROT_ERR, 100*4882a593Smuzhiyun BD9571MWV_IRQ_GP, 101*4882a593Smuzhiyun BD9571MWV_IRQ_128H_OF, 102*4882a593Smuzhiyun BD9571MWV_IRQ_WDT_OF, 103*4882a593Smuzhiyun BD9571MWV_IRQ_BKUP_TRG, 104*4882a593Smuzhiyun }; 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /** 107*4882a593Smuzhiyun * struct bd9571mwv - state holder for the bd9571mwv driver 108*4882a593Smuzhiyun * 109*4882a593Smuzhiyun * Device data may be used to access the BD9571MWV chip 110*4882a593Smuzhiyun */ 111*4882a593Smuzhiyun struct bd9571mwv { 112*4882a593Smuzhiyun struct device *dev; 113*4882a593Smuzhiyun struct regmap *regmap; 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun /* IRQ Data */ 116*4882a593Smuzhiyun int irq; 117*4882a593Smuzhiyun struct regmap_irq_chip_data *irq_data; 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #endif /* __LINUX_MFD_BD9571MWV_H */ 121