xref: /OK3568_Linux_fs/kernel/include/linux/mfd/axp20x.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Functions and registers to access AXP20X power management chip.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright (C) 2013, Carlo Caione <carlo@caione.org>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef __LINUX_MFD_AXP20X_H
9*4882a593Smuzhiyun #define __LINUX_MFD_AXP20X_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <linux/regmap.h>
12*4882a593Smuzhiyun 
13*4882a593Smuzhiyun enum axp20x_variants {
14*4882a593Smuzhiyun 	AXP152_ID = 0,
15*4882a593Smuzhiyun 	AXP202_ID,
16*4882a593Smuzhiyun 	AXP209_ID,
17*4882a593Smuzhiyun 	AXP221_ID,
18*4882a593Smuzhiyun 	AXP223_ID,
19*4882a593Smuzhiyun 	AXP288_ID,
20*4882a593Smuzhiyun 	AXP803_ID,
21*4882a593Smuzhiyun 	AXP806_ID,
22*4882a593Smuzhiyun 	AXP809_ID,
23*4882a593Smuzhiyun 	AXP813_ID,
24*4882a593Smuzhiyun 	NR_AXP20X_VARIANTS,
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #define AXP20X_DATACACHE(m)		(0x04 + (m))
28*4882a593Smuzhiyun 
29*4882a593Smuzhiyun /* Power supply */
30*4882a593Smuzhiyun #define AXP152_PWR_OP_MODE		0x01
31*4882a593Smuzhiyun #define AXP152_LDO3456_DC1234_CTRL	0x12
32*4882a593Smuzhiyun #define AXP152_ALDO_OP_MODE		0x13
33*4882a593Smuzhiyun #define AXP152_LDO0_CTRL		0x15
34*4882a593Smuzhiyun #define AXP152_DCDC2_V_OUT		0x23
35*4882a593Smuzhiyun #define AXP152_DCDC2_V_RAMP		0x25
36*4882a593Smuzhiyun #define AXP152_DCDC1_V_OUT		0x26
37*4882a593Smuzhiyun #define AXP152_DCDC3_V_OUT		0x27
38*4882a593Smuzhiyun #define AXP152_ALDO12_V_OUT		0x28
39*4882a593Smuzhiyun #define AXP152_DLDO1_V_OUT		0x29
40*4882a593Smuzhiyun #define AXP152_DLDO2_V_OUT		0x2a
41*4882a593Smuzhiyun #define AXP152_DCDC4_V_OUT		0x2b
42*4882a593Smuzhiyun #define AXP152_V_OFF			0x31
43*4882a593Smuzhiyun #define AXP152_OFF_CTRL			0x32
44*4882a593Smuzhiyun #define AXP152_PEK_KEY			0x36
45*4882a593Smuzhiyun #define AXP152_DCDC_FREQ		0x37
46*4882a593Smuzhiyun #define AXP152_DCDC_MODE		0x80
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define AXP20X_PWR_INPUT_STATUS		0x00
49*4882a593Smuzhiyun #define AXP20X_PWR_OP_MODE		0x01
50*4882a593Smuzhiyun #define AXP20X_USB_OTG_STATUS		0x02
51*4882a593Smuzhiyun #define AXP20X_PWR_OUT_CTRL		0x12
52*4882a593Smuzhiyun #define AXP20X_DCDC2_V_OUT		0x23
53*4882a593Smuzhiyun #define AXP20X_DCDC2_LDO3_V_RAMP	0x25
54*4882a593Smuzhiyun #define AXP20X_DCDC3_V_OUT		0x27
55*4882a593Smuzhiyun #define AXP20X_LDO24_V_OUT		0x28
56*4882a593Smuzhiyun #define AXP20X_LDO3_V_OUT		0x29
57*4882a593Smuzhiyun #define AXP20X_VBUS_IPSOUT_MGMT		0x30
58*4882a593Smuzhiyun #define AXP20X_V_OFF			0x31
59*4882a593Smuzhiyun #define AXP20X_OFF_CTRL			0x32
60*4882a593Smuzhiyun #define AXP20X_CHRG_CTRL1		0x33
61*4882a593Smuzhiyun #define AXP20X_CHRG_CTRL2		0x34
62*4882a593Smuzhiyun #define AXP20X_CHRG_BAK_CTRL		0x35
63*4882a593Smuzhiyun #define AXP20X_PEK_KEY			0x36
64*4882a593Smuzhiyun #define AXP20X_DCDC_FREQ		0x37
65*4882a593Smuzhiyun #define AXP20X_V_LTF_CHRG		0x38
66*4882a593Smuzhiyun #define AXP20X_V_HTF_CHRG		0x39
67*4882a593Smuzhiyun #define AXP20X_APS_WARN_L1		0x3a
68*4882a593Smuzhiyun #define AXP20X_APS_WARN_L2		0x3b
69*4882a593Smuzhiyun #define AXP20X_V_LTF_DISCHRG		0x3c
70*4882a593Smuzhiyun #define AXP20X_V_HTF_DISCHRG		0x3d
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun #define AXP22X_PWR_OUT_CTRL1		0x10
73*4882a593Smuzhiyun #define AXP22X_PWR_OUT_CTRL2		0x12
74*4882a593Smuzhiyun #define AXP22X_PWR_OUT_CTRL3		0x13
75*4882a593Smuzhiyun #define AXP22X_DLDO1_V_OUT		0x15
76*4882a593Smuzhiyun #define AXP22X_DLDO2_V_OUT		0x16
77*4882a593Smuzhiyun #define AXP22X_DLDO3_V_OUT		0x17
78*4882a593Smuzhiyun #define AXP22X_DLDO4_V_OUT		0x18
79*4882a593Smuzhiyun #define AXP22X_ELDO1_V_OUT		0x19
80*4882a593Smuzhiyun #define AXP22X_ELDO2_V_OUT		0x1a
81*4882a593Smuzhiyun #define AXP22X_ELDO3_V_OUT		0x1b
82*4882a593Smuzhiyun #define AXP22X_DC5LDO_V_OUT		0x1c
83*4882a593Smuzhiyun #define AXP22X_DCDC1_V_OUT		0x21
84*4882a593Smuzhiyun #define AXP22X_DCDC2_V_OUT		0x22
85*4882a593Smuzhiyun #define AXP22X_DCDC3_V_OUT		0x23
86*4882a593Smuzhiyun #define AXP22X_DCDC4_V_OUT		0x24
87*4882a593Smuzhiyun #define AXP22X_DCDC5_V_OUT		0x25
88*4882a593Smuzhiyun #define AXP22X_DCDC23_V_RAMP_CTRL	0x27
89*4882a593Smuzhiyun #define AXP22X_ALDO1_V_OUT		0x28
90*4882a593Smuzhiyun #define AXP22X_ALDO2_V_OUT		0x29
91*4882a593Smuzhiyun #define AXP22X_ALDO3_V_OUT		0x2a
92*4882a593Smuzhiyun #define AXP22X_CHRG_CTRL3		0x35
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define AXP806_STARTUP_SRC		0x00
95*4882a593Smuzhiyun #define AXP806_CHIP_ID			0x03
96*4882a593Smuzhiyun #define AXP806_PWR_OUT_CTRL1		0x10
97*4882a593Smuzhiyun #define AXP806_PWR_OUT_CTRL2		0x11
98*4882a593Smuzhiyun #define AXP806_DCDCA_V_CTRL		0x12
99*4882a593Smuzhiyun #define AXP806_DCDCB_V_CTRL		0x13
100*4882a593Smuzhiyun #define AXP806_DCDCC_V_CTRL		0x14
101*4882a593Smuzhiyun #define AXP806_DCDCD_V_CTRL		0x15
102*4882a593Smuzhiyun #define AXP806_DCDCE_V_CTRL		0x16
103*4882a593Smuzhiyun #define AXP806_ALDO1_V_CTRL		0x17
104*4882a593Smuzhiyun #define AXP806_ALDO2_V_CTRL		0x18
105*4882a593Smuzhiyun #define AXP806_ALDO3_V_CTRL		0x19
106*4882a593Smuzhiyun #define AXP806_DCDC_MODE_CTRL1		0x1a
107*4882a593Smuzhiyun #define AXP806_DCDC_MODE_CTRL2		0x1b
108*4882a593Smuzhiyun #define AXP806_DCDC_FREQ_CTRL		0x1c
109*4882a593Smuzhiyun #define AXP806_BLDO1_V_CTRL		0x20
110*4882a593Smuzhiyun #define AXP806_BLDO2_V_CTRL		0x21
111*4882a593Smuzhiyun #define AXP806_BLDO3_V_CTRL		0x22
112*4882a593Smuzhiyun #define AXP806_BLDO4_V_CTRL		0x23
113*4882a593Smuzhiyun #define AXP806_CLDO1_V_CTRL		0x24
114*4882a593Smuzhiyun #define AXP806_CLDO2_V_CTRL		0x25
115*4882a593Smuzhiyun #define AXP806_CLDO3_V_CTRL		0x26
116*4882a593Smuzhiyun #define AXP806_VREF_TEMP_WARN_L		0xf3
117*4882a593Smuzhiyun #define AXP806_BUS_ADDR_EXT		0xfe
118*4882a593Smuzhiyun #define AXP806_REG_ADDR_EXT		0xff
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun #define AXP803_POLYPHASE_CTRL		0x14
121*4882a593Smuzhiyun #define AXP803_FLDO1_V_OUT		0x1c
122*4882a593Smuzhiyun #define AXP803_FLDO2_V_OUT		0x1d
123*4882a593Smuzhiyun #define AXP803_DCDC1_V_OUT		0x20
124*4882a593Smuzhiyun #define AXP803_DCDC2_V_OUT		0x21
125*4882a593Smuzhiyun #define AXP803_DCDC3_V_OUT		0x22
126*4882a593Smuzhiyun #define AXP803_DCDC4_V_OUT		0x23
127*4882a593Smuzhiyun #define AXP803_DCDC5_V_OUT		0x24
128*4882a593Smuzhiyun #define AXP803_DCDC6_V_OUT		0x25
129*4882a593Smuzhiyun #define AXP803_DCDC_FREQ_CTRL		0x3b
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /* Other DCDC regulator control registers are the same as AXP803 */
132*4882a593Smuzhiyun #define AXP813_DCDC7_V_OUT		0x26
133*4882a593Smuzhiyun 
134*4882a593Smuzhiyun /* Interrupt */
135*4882a593Smuzhiyun #define AXP152_IRQ1_EN			0x40
136*4882a593Smuzhiyun #define AXP152_IRQ2_EN			0x41
137*4882a593Smuzhiyun #define AXP152_IRQ3_EN			0x42
138*4882a593Smuzhiyun #define AXP152_IRQ1_STATE		0x48
139*4882a593Smuzhiyun #define AXP152_IRQ2_STATE		0x49
140*4882a593Smuzhiyun #define AXP152_IRQ3_STATE		0x4a
141*4882a593Smuzhiyun 
142*4882a593Smuzhiyun #define AXP20X_IRQ1_EN			0x40
143*4882a593Smuzhiyun #define AXP20X_IRQ2_EN			0x41
144*4882a593Smuzhiyun #define AXP20X_IRQ3_EN			0x42
145*4882a593Smuzhiyun #define AXP20X_IRQ4_EN			0x43
146*4882a593Smuzhiyun #define AXP20X_IRQ5_EN			0x44
147*4882a593Smuzhiyun #define AXP20X_IRQ6_EN			0x45
148*4882a593Smuzhiyun #define AXP20X_IRQ1_STATE		0x48
149*4882a593Smuzhiyun #define AXP20X_IRQ2_STATE		0x49
150*4882a593Smuzhiyun #define AXP20X_IRQ3_STATE		0x4a
151*4882a593Smuzhiyun #define AXP20X_IRQ4_STATE		0x4b
152*4882a593Smuzhiyun #define AXP20X_IRQ5_STATE		0x4c
153*4882a593Smuzhiyun #define AXP20X_IRQ6_STATE		0x4d
154*4882a593Smuzhiyun 
155*4882a593Smuzhiyun /* ADC */
156*4882a593Smuzhiyun #define AXP20X_ACIN_V_ADC_H		0x56
157*4882a593Smuzhiyun #define AXP20X_ACIN_V_ADC_L		0x57
158*4882a593Smuzhiyun #define AXP20X_ACIN_I_ADC_H		0x58
159*4882a593Smuzhiyun #define AXP20X_ACIN_I_ADC_L		0x59
160*4882a593Smuzhiyun #define AXP20X_VBUS_V_ADC_H		0x5a
161*4882a593Smuzhiyun #define AXP20X_VBUS_V_ADC_L		0x5b
162*4882a593Smuzhiyun #define AXP20X_VBUS_I_ADC_H		0x5c
163*4882a593Smuzhiyun #define AXP20X_VBUS_I_ADC_L		0x5d
164*4882a593Smuzhiyun #define AXP20X_TEMP_ADC_H		0x5e
165*4882a593Smuzhiyun #define AXP20X_TEMP_ADC_L		0x5f
166*4882a593Smuzhiyun #define AXP20X_TS_IN_H			0x62
167*4882a593Smuzhiyun #define AXP20X_TS_IN_L			0x63
168*4882a593Smuzhiyun #define AXP20X_GPIO0_V_ADC_H		0x64
169*4882a593Smuzhiyun #define AXP20X_GPIO0_V_ADC_L		0x65
170*4882a593Smuzhiyun #define AXP20X_GPIO1_V_ADC_H		0x66
171*4882a593Smuzhiyun #define AXP20X_GPIO1_V_ADC_L		0x67
172*4882a593Smuzhiyun #define AXP20X_PWR_BATT_H		0x70
173*4882a593Smuzhiyun #define AXP20X_PWR_BATT_M		0x71
174*4882a593Smuzhiyun #define AXP20X_PWR_BATT_L		0x72
175*4882a593Smuzhiyun #define AXP20X_BATT_V_H			0x78
176*4882a593Smuzhiyun #define AXP20X_BATT_V_L			0x79
177*4882a593Smuzhiyun #define AXP20X_BATT_CHRG_I_H		0x7a
178*4882a593Smuzhiyun #define AXP20X_BATT_CHRG_I_L		0x7b
179*4882a593Smuzhiyun #define AXP20X_BATT_DISCHRG_I_H		0x7c
180*4882a593Smuzhiyun #define AXP20X_BATT_DISCHRG_I_L		0x7d
181*4882a593Smuzhiyun #define AXP20X_IPSOUT_V_HIGH_H		0x7e
182*4882a593Smuzhiyun #define AXP20X_IPSOUT_V_HIGH_L		0x7f
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun /* Power supply */
185*4882a593Smuzhiyun #define AXP20X_DCDC_MODE		0x80
186*4882a593Smuzhiyun #define AXP20X_ADC_EN1			0x82
187*4882a593Smuzhiyun #define AXP20X_ADC_EN2			0x83
188*4882a593Smuzhiyun #define AXP20X_ADC_RATE			0x84
189*4882a593Smuzhiyun #define AXP20X_GPIO10_IN_RANGE		0x85
190*4882a593Smuzhiyun #define AXP20X_GPIO1_ADC_IRQ_RIS	0x86
191*4882a593Smuzhiyun #define AXP20X_GPIO1_ADC_IRQ_FAL	0x87
192*4882a593Smuzhiyun #define AXP20X_TIMER_CTRL		0x8a
193*4882a593Smuzhiyun #define AXP20X_VBUS_MON			0x8b
194*4882a593Smuzhiyun #define AXP20X_OVER_TMP			0x8f
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun #define AXP22X_PWREN_CTRL1		0x8c
197*4882a593Smuzhiyun #define AXP22X_PWREN_CTRL2		0x8d
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun /* GPIO */
200*4882a593Smuzhiyun #define AXP152_GPIO0_CTRL		0x90
201*4882a593Smuzhiyun #define AXP152_GPIO1_CTRL		0x91
202*4882a593Smuzhiyun #define AXP152_GPIO2_CTRL		0x92
203*4882a593Smuzhiyun #define AXP152_GPIO3_CTRL		0x93
204*4882a593Smuzhiyun #define AXP152_LDOGPIO2_V_OUT		0x96
205*4882a593Smuzhiyun #define AXP152_GPIO_INPUT		0x97
206*4882a593Smuzhiyun #define AXP152_PWM0_FREQ_X		0x98
207*4882a593Smuzhiyun #define AXP152_PWM0_FREQ_Y		0x99
208*4882a593Smuzhiyun #define AXP152_PWM0_DUTY_CYCLE		0x9a
209*4882a593Smuzhiyun #define AXP152_PWM1_FREQ_X		0x9b
210*4882a593Smuzhiyun #define AXP152_PWM1_FREQ_Y		0x9c
211*4882a593Smuzhiyun #define AXP152_PWM1_DUTY_CYCLE		0x9d
212*4882a593Smuzhiyun 
213*4882a593Smuzhiyun #define AXP20X_GPIO0_CTRL		0x90
214*4882a593Smuzhiyun #define AXP20X_LDO5_V_OUT		0x91
215*4882a593Smuzhiyun #define AXP20X_GPIO1_CTRL		0x92
216*4882a593Smuzhiyun #define AXP20X_GPIO2_CTRL		0x93
217*4882a593Smuzhiyun #define AXP20X_GPIO20_SS		0x94
218*4882a593Smuzhiyun #define AXP20X_GPIO3_CTRL		0x95
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #define AXP22X_LDO_IO0_V_OUT		0x91
221*4882a593Smuzhiyun #define AXP22X_LDO_IO1_V_OUT		0x93
222*4882a593Smuzhiyun #define AXP22X_GPIO_STATE		0x94
223*4882a593Smuzhiyun #define AXP22X_GPIO_PULL_DOWN		0x95
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun /* Battery */
226*4882a593Smuzhiyun #define AXP20X_CHRG_CC_31_24		0xb0
227*4882a593Smuzhiyun #define AXP20X_CHRG_CC_23_16		0xb1
228*4882a593Smuzhiyun #define AXP20X_CHRG_CC_15_8		0xb2
229*4882a593Smuzhiyun #define AXP20X_CHRG_CC_7_0		0xb3
230*4882a593Smuzhiyun #define AXP20X_DISCHRG_CC_31_24		0xb4
231*4882a593Smuzhiyun #define AXP20X_DISCHRG_CC_23_16		0xb5
232*4882a593Smuzhiyun #define AXP20X_DISCHRG_CC_15_8		0xb6
233*4882a593Smuzhiyun #define AXP20X_DISCHRG_CC_7_0		0xb7
234*4882a593Smuzhiyun #define AXP20X_CC_CTRL			0xb8
235*4882a593Smuzhiyun #define AXP20X_FG_RES			0xb9
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun /* OCV */
238*4882a593Smuzhiyun #define AXP20X_RDC_H			0xba
239*4882a593Smuzhiyun #define AXP20X_RDC_L			0xbb
240*4882a593Smuzhiyun #define AXP20X_OCV(m)			(0xc0 + (m))
241*4882a593Smuzhiyun #define AXP20X_OCV_MAX			0xf
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun /* AXP22X specific registers */
244*4882a593Smuzhiyun #define AXP22X_PMIC_TEMP_H		0x56
245*4882a593Smuzhiyun #define AXP22X_PMIC_TEMP_L		0x57
246*4882a593Smuzhiyun #define AXP22X_TS_ADC_H			0x58
247*4882a593Smuzhiyun #define AXP22X_TS_ADC_L			0x59
248*4882a593Smuzhiyun #define AXP22X_BATLOW_THRES1		0xe6
249*4882a593Smuzhiyun 
250*4882a593Smuzhiyun /* AXP288/AXP803 specific registers */
251*4882a593Smuzhiyun #define AXP288_POWER_REASON		0x02
252*4882a593Smuzhiyun #define AXP288_BC_GLOBAL		0x2c
253*4882a593Smuzhiyun #define AXP288_BC_VBUS_CNTL		0x2d
254*4882a593Smuzhiyun #define AXP288_BC_USB_STAT		0x2e
255*4882a593Smuzhiyun #define AXP288_BC_DET_STAT		0x2f
256*4882a593Smuzhiyun #define AXP288_PMIC_ADC_H               0x56
257*4882a593Smuzhiyun #define AXP288_PMIC_ADC_L               0x57
258*4882a593Smuzhiyun #define AXP288_TS_ADC_H			0x58
259*4882a593Smuzhiyun #define AXP288_TS_ADC_L			0x59
260*4882a593Smuzhiyun #define AXP288_GP_ADC_H			0x5a
261*4882a593Smuzhiyun #define AXP288_GP_ADC_L			0x5b
262*4882a593Smuzhiyun #define AXP288_ADC_TS_PIN_CTRL          0x84
263*4882a593Smuzhiyun #define AXP288_RT_BATT_V_H		0xa0
264*4882a593Smuzhiyun #define AXP288_RT_BATT_V_L		0xa1
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun #define AXP813_ACIN_PATH_CTRL		0x3a
267*4882a593Smuzhiyun #define AXP813_ADC_RATE			0x85
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun /* Fuel Gauge */
270*4882a593Smuzhiyun #define AXP288_FG_RDC1_REG          0xba
271*4882a593Smuzhiyun #define AXP288_FG_RDC0_REG          0xbb
272*4882a593Smuzhiyun #define AXP288_FG_OCVH_REG          0xbc
273*4882a593Smuzhiyun #define AXP288_FG_OCVL_REG          0xbd
274*4882a593Smuzhiyun #define AXP288_FG_OCV_CURVE_REG     0xc0
275*4882a593Smuzhiyun #define AXP288_FG_DES_CAP1_REG      0xe0
276*4882a593Smuzhiyun #define AXP288_FG_DES_CAP0_REG      0xe1
277*4882a593Smuzhiyun #define AXP288_FG_CC_MTR1_REG       0xe2
278*4882a593Smuzhiyun #define AXP288_FG_CC_MTR0_REG       0xe3
279*4882a593Smuzhiyun #define AXP288_FG_OCV_CAP_REG       0xe4
280*4882a593Smuzhiyun #define AXP288_FG_CC_CAP_REG        0xe5
281*4882a593Smuzhiyun #define AXP288_FG_LOW_CAP_REG       0xe6
282*4882a593Smuzhiyun #define AXP288_FG_TUNE0             0xe8
283*4882a593Smuzhiyun #define AXP288_FG_TUNE1             0xe9
284*4882a593Smuzhiyun #define AXP288_FG_TUNE2             0xea
285*4882a593Smuzhiyun #define AXP288_FG_TUNE3             0xeb
286*4882a593Smuzhiyun #define AXP288_FG_TUNE4             0xec
287*4882a593Smuzhiyun #define AXP288_FG_TUNE5             0xed
288*4882a593Smuzhiyun 
289*4882a593Smuzhiyun /* Regulators IDs */
290*4882a593Smuzhiyun enum {
291*4882a593Smuzhiyun 	AXP20X_LDO1 = 0,
292*4882a593Smuzhiyun 	AXP20X_LDO2,
293*4882a593Smuzhiyun 	AXP20X_LDO3,
294*4882a593Smuzhiyun 	AXP20X_LDO4,
295*4882a593Smuzhiyun 	AXP20X_LDO5,
296*4882a593Smuzhiyun 	AXP20X_DCDC2,
297*4882a593Smuzhiyun 	AXP20X_DCDC3,
298*4882a593Smuzhiyun 	AXP20X_REG_ID_MAX,
299*4882a593Smuzhiyun };
300*4882a593Smuzhiyun 
301*4882a593Smuzhiyun enum {
302*4882a593Smuzhiyun 	AXP22X_DCDC1 = 0,
303*4882a593Smuzhiyun 	AXP22X_DCDC2,
304*4882a593Smuzhiyun 	AXP22X_DCDC3,
305*4882a593Smuzhiyun 	AXP22X_DCDC4,
306*4882a593Smuzhiyun 	AXP22X_DCDC5,
307*4882a593Smuzhiyun 	AXP22X_DC1SW,
308*4882a593Smuzhiyun 	AXP22X_DC5LDO,
309*4882a593Smuzhiyun 	AXP22X_ALDO1,
310*4882a593Smuzhiyun 	AXP22X_ALDO2,
311*4882a593Smuzhiyun 	AXP22X_ALDO3,
312*4882a593Smuzhiyun 	AXP22X_ELDO1,
313*4882a593Smuzhiyun 	AXP22X_ELDO2,
314*4882a593Smuzhiyun 	AXP22X_ELDO3,
315*4882a593Smuzhiyun 	AXP22X_DLDO1,
316*4882a593Smuzhiyun 	AXP22X_DLDO2,
317*4882a593Smuzhiyun 	AXP22X_DLDO3,
318*4882a593Smuzhiyun 	AXP22X_DLDO4,
319*4882a593Smuzhiyun 	AXP22X_RTC_LDO,
320*4882a593Smuzhiyun 	AXP22X_LDO_IO0,
321*4882a593Smuzhiyun 	AXP22X_LDO_IO1,
322*4882a593Smuzhiyun 	AXP22X_REG_ID_MAX,
323*4882a593Smuzhiyun };
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun enum {
326*4882a593Smuzhiyun 	AXP806_DCDCA = 0,
327*4882a593Smuzhiyun 	AXP806_DCDCB,
328*4882a593Smuzhiyun 	AXP806_DCDCC,
329*4882a593Smuzhiyun 	AXP806_DCDCD,
330*4882a593Smuzhiyun 	AXP806_DCDCE,
331*4882a593Smuzhiyun 	AXP806_ALDO1,
332*4882a593Smuzhiyun 	AXP806_ALDO2,
333*4882a593Smuzhiyun 	AXP806_ALDO3,
334*4882a593Smuzhiyun 	AXP806_BLDO1,
335*4882a593Smuzhiyun 	AXP806_BLDO2,
336*4882a593Smuzhiyun 	AXP806_BLDO3,
337*4882a593Smuzhiyun 	AXP806_BLDO4,
338*4882a593Smuzhiyun 	AXP806_CLDO1,
339*4882a593Smuzhiyun 	AXP806_CLDO2,
340*4882a593Smuzhiyun 	AXP806_CLDO3,
341*4882a593Smuzhiyun 	AXP806_SW,
342*4882a593Smuzhiyun 	AXP806_REG_ID_MAX,
343*4882a593Smuzhiyun };
344*4882a593Smuzhiyun 
345*4882a593Smuzhiyun enum {
346*4882a593Smuzhiyun 	AXP809_DCDC1 = 0,
347*4882a593Smuzhiyun 	AXP809_DCDC2,
348*4882a593Smuzhiyun 	AXP809_DCDC3,
349*4882a593Smuzhiyun 	AXP809_DCDC4,
350*4882a593Smuzhiyun 	AXP809_DCDC5,
351*4882a593Smuzhiyun 	AXP809_DC1SW,
352*4882a593Smuzhiyun 	AXP809_DC5LDO,
353*4882a593Smuzhiyun 	AXP809_ALDO1,
354*4882a593Smuzhiyun 	AXP809_ALDO2,
355*4882a593Smuzhiyun 	AXP809_ALDO3,
356*4882a593Smuzhiyun 	AXP809_ELDO1,
357*4882a593Smuzhiyun 	AXP809_ELDO2,
358*4882a593Smuzhiyun 	AXP809_ELDO3,
359*4882a593Smuzhiyun 	AXP809_DLDO1,
360*4882a593Smuzhiyun 	AXP809_DLDO2,
361*4882a593Smuzhiyun 	AXP809_RTC_LDO,
362*4882a593Smuzhiyun 	AXP809_LDO_IO0,
363*4882a593Smuzhiyun 	AXP809_LDO_IO1,
364*4882a593Smuzhiyun 	AXP809_SW,
365*4882a593Smuzhiyun 	AXP809_REG_ID_MAX,
366*4882a593Smuzhiyun };
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun enum {
369*4882a593Smuzhiyun 	AXP803_DCDC1 = 0,
370*4882a593Smuzhiyun 	AXP803_DCDC2,
371*4882a593Smuzhiyun 	AXP803_DCDC3,
372*4882a593Smuzhiyun 	AXP803_DCDC4,
373*4882a593Smuzhiyun 	AXP803_DCDC5,
374*4882a593Smuzhiyun 	AXP803_DCDC6,
375*4882a593Smuzhiyun 	AXP803_DC1SW,
376*4882a593Smuzhiyun 	AXP803_ALDO1,
377*4882a593Smuzhiyun 	AXP803_ALDO2,
378*4882a593Smuzhiyun 	AXP803_ALDO3,
379*4882a593Smuzhiyun 	AXP803_DLDO1,
380*4882a593Smuzhiyun 	AXP803_DLDO2,
381*4882a593Smuzhiyun 	AXP803_DLDO3,
382*4882a593Smuzhiyun 	AXP803_DLDO4,
383*4882a593Smuzhiyun 	AXP803_ELDO1,
384*4882a593Smuzhiyun 	AXP803_ELDO2,
385*4882a593Smuzhiyun 	AXP803_ELDO3,
386*4882a593Smuzhiyun 	AXP803_FLDO1,
387*4882a593Smuzhiyun 	AXP803_FLDO2,
388*4882a593Smuzhiyun 	AXP803_RTC_LDO,
389*4882a593Smuzhiyun 	AXP803_LDO_IO0,
390*4882a593Smuzhiyun 	AXP803_LDO_IO1,
391*4882a593Smuzhiyun 	AXP803_REG_ID_MAX,
392*4882a593Smuzhiyun };
393*4882a593Smuzhiyun 
394*4882a593Smuzhiyun enum {
395*4882a593Smuzhiyun 	AXP813_DCDC1 = 0,
396*4882a593Smuzhiyun 	AXP813_DCDC2,
397*4882a593Smuzhiyun 	AXP813_DCDC3,
398*4882a593Smuzhiyun 	AXP813_DCDC4,
399*4882a593Smuzhiyun 	AXP813_DCDC5,
400*4882a593Smuzhiyun 	AXP813_DCDC6,
401*4882a593Smuzhiyun 	AXP813_DCDC7,
402*4882a593Smuzhiyun 	AXP813_ALDO1,
403*4882a593Smuzhiyun 	AXP813_ALDO2,
404*4882a593Smuzhiyun 	AXP813_ALDO3,
405*4882a593Smuzhiyun 	AXP813_DLDO1,
406*4882a593Smuzhiyun 	AXP813_DLDO2,
407*4882a593Smuzhiyun 	AXP813_DLDO3,
408*4882a593Smuzhiyun 	AXP813_DLDO4,
409*4882a593Smuzhiyun 	AXP813_ELDO1,
410*4882a593Smuzhiyun 	AXP813_ELDO2,
411*4882a593Smuzhiyun 	AXP813_ELDO3,
412*4882a593Smuzhiyun 	AXP813_FLDO1,
413*4882a593Smuzhiyun 	AXP813_FLDO2,
414*4882a593Smuzhiyun 	AXP813_FLDO3,
415*4882a593Smuzhiyun 	AXP813_RTC_LDO,
416*4882a593Smuzhiyun 	AXP813_LDO_IO0,
417*4882a593Smuzhiyun 	AXP813_LDO_IO1,
418*4882a593Smuzhiyun 	AXP813_SW,
419*4882a593Smuzhiyun 	AXP813_REG_ID_MAX,
420*4882a593Smuzhiyun };
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun /* IRQs */
423*4882a593Smuzhiyun enum {
424*4882a593Smuzhiyun 	AXP152_IRQ_LDO0IN_CONNECT = 1,
425*4882a593Smuzhiyun 	AXP152_IRQ_LDO0IN_REMOVAL,
426*4882a593Smuzhiyun 	AXP152_IRQ_ALDO0IN_CONNECT,
427*4882a593Smuzhiyun 	AXP152_IRQ_ALDO0IN_REMOVAL,
428*4882a593Smuzhiyun 	AXP152_IRQ_DCDC1_V_LOW,
429*4882a593Smuzhiyun 	AXP152_IRQ_DCDC2_V_LOW,
430*4882a593Smuzhiyun 	AXP152_IRQ_DCDC3_V_LOW,
431*4882a593Smuzhiyun 	AXP152_IRQ_DCDC4_V_LOW,
432*4882a593Smuzhiyun 	AXP152_IRQ_PEK_SHORT,
433*4882a593Smuzhiyun 	AXP152_IRQ_PEK_LONG,
434*4882a593Smuzhiyun 	AXP152_IRQ_TIMER,
435*4882a593Smuzhiyun 	AXP152_IRQ_PEK_RIS_EDGE,
436*4882a593Smuzhiyun 	AXP152_IRQ_PEK_FAL_EDGE,
437*4882a593Smuzhiyun 	AXP152_IRQ_GPIO3_INPUT,
438*4882a593Smuzhiyun 	AXP152_IRQ_GPIO2_INPUT,
439*4882a593Smuzhiyun 	AXP152_IRQ_GPIO1_INPUT,
440*4882a593Smuzhiyun 	AXP152_IRQ_GPIO0_INPUT,
441*4882a593Smuzhiyun };
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun enum {
444*4882a593Smuzhiyun 	AXP20X_IRQ_ACIN_OVER_V = 1,
445*4882a593Smuzhiyun 	AXP20X_IRQ_ACIN_PLUGIN,
446*4882a593Smuzhiyun 	AXP20X_IRQ_ACIN_REMOVAL,
447*4882a593Smuzhiyun 	AXP20X_IRQ_VBUS_OVER_V,
448*4882a593Smuzhiyun 	AXP20X_IRQ_VBUS_PLUGIN,
449*4882a593Smuzhiyun 	AXP20X_IRQ_VBUS_REMOVAL,
450*4882a593Smuzhiyun 	AXP20X_IRQ_VBUS_V_LOW,
451*4882a593Smuzhiyun 	AXP20X_IRQ_BATT_PLUGIN,
452*4882a593Smuzhiyun 	AXP20X_IRQ_BATT_REMOVAL,
453*4882a593Smuzhiyun 	AXP20X_IRQ_BATT_ENT_ACT_MODE,
454*4882a593Smuzhiyun 	AXP20X_IRQ_BATT_EXIT_ACT_MODE,
455*4882a593Smuzhiyun 	AXP20X_IRQ_CHARG,
456*4882a593Smuzhiyun 	AXP20X_IRQ_CHARG_DONE,
457*4882a593Smuzhiyun 	AXP20X_IRQ_BATT_TEMP_HIGH,
458*4882a593Smuzhiyun 	AXP20X_IRQ_BATT_TEMP_LOW,
459*4882a593Smuzhiyun 	AXP20X_IRQ_DIE_TEMP_HIGH,
460*4882a593Smuzhiyun 	AXP20X_IRQ_CHARG_I_LOW,
461*4882a593Smuzhiyun 	AXP20X_IRQ_DCDC1_V_LONG,
462*4882a593Smuzhiyun 	AXP20X_IRQ_DCDC2_V_LONG,
463*4882a593Smuzhiyun 	AXP20X_IRQ_DCDC3_V_LONG,
464*4882a593Smuzhiyun 	AXP20X_IRQ_PEK_SHORT = 22,
465*4882a593Smuzhiyun 	AXP20X_IRQ_PEK_LONG,
466*4882a593Smuzhiyun 	AXP20X_IRQ_N_OE_PWR_ON,
467*4882a593Smuzhiyun 	AXP20X_IRQ_N_OE_PWR_OFF,
468*4882a593Smuzhiyun 	AXP20X_IRQ_VBUS_VALID,
469*4882a593Smuzhiyun 	AXP20X_IRQ_VBUS_NOT_VALID,
470*4882a593Smuzhiyun 	AXP20X_IRQ_VBUS_SESS_VALID,
471*4882a593Smuzhiyun 	AXP20X_IRQ_VBUS_SESS_END,
472*4882a593Smuzhiyun 	AXP20X_IRQ_LOW_PWR_LVL1,
473*4882a593Smuzhiyun 	AXP20X_IRQ_LOW_PWR_LVL2,
474*4882a593Smuzhiyun 	AXP20X_IRQ_TIMER,
475*4882a593Smuzhiyun 	AXP20X_IRQ_PEK_RIS_EDGE,
476*4882a593Smuzhiyun 	AXP20X_IRQ_PEK_FAL_EDGE,
477*4882a593Smuzhiyun 	AXP20X_IRQ_GPIO3_INPUT,
478*4882a593Smuzhiyun 	AXP20X_IRQ_GPIO2_INPUT,
479*4882a593Smuzhiyun 	AXP20X_IRQ_GPIO1_INPUT,
480*4882a593Smuzhiyun 	AXP20X_IRQ_GPIO0_INPUT,
481*4882a593Smuzhiyun };
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun enum axp22x_irqs {
484*4882a593Smuzhiyun 	AXP22X_IRQ_ACIN_OVER_V = 1,
485*4882a593Smuzhiyun 	AXP22X_IRQ_ACIN_PLUGIN,
486*4882a593Smuzhiyun 	AXP22X_IRQ_ACIN_REMOVAL,
487*4882a593Smuzhiyun 	AXP22X_IRQ_VBUS_OVER_V,
488*4882a593Smuzhiyun 	AXP22X_IRQ_VBUS_PLUGIN,
489*4882a593Smuzhiyun 	AXP22X_IRQ_VBUS_REMOVAL,
490*4882a593Smuzhiyun 	AXP22X_IRQ_VBUS_V_LOW,
491*4882a593Smuzhiyun 	AXP22X_IRQ_BATT_PLUGIN,
492*4882a593Smuzhiyun 	AXP22X_IRQ_BATT_REMOVAL,
493*4882a593Smuzhiyun 	AXP22X_IRQ_BATT_ENT_ACT_MODE,
494*4882a593Smuzhiyun 	AXP22X_IRQ_BATT_EXIT_ACT_MODE,
495*4882a593Smuzhiyun 	AXP22X_IRQ_CHARG,
496*4882a593Smuzhiyun 	AXP22X_IRQ_CHARG_DONE,
497*4882a593Smuzhiyun 	AXP22X_IRQ_BATT_TEMP_HIGH,
498*4882a593Smuzhiyun 	AXP22X_IRQ_BATT_TEMP_LOW,
499*4882a593Smuzhiyun 	AXP22X_IRQ_DIE_TEMP_HIGH,
500*4882a593Smuzhiyun 	AXP22X_IRQ_PEK_SHORT,
501*4882a593Smuzhiyun 	AXP22X_IRQ_PEK_LONG,
502*4882a593Smuzhiyun 	AXP22X_IRQ_LOW_PWR_LVL1,
503*4882a593Smuzhiyun 	AXP22X_IRQ_LOW_PWR_LVL2,
504*4882a593Smuzhiyun 	AXP22X_IRQ_TIMER,
505*4882a593Smuzhiyun 	AXP22X_IRQ_PEK_RIS_EDGE,
506*4882a593Smuzhiyun 	AXP22X_IRQ_PEK_FAL_EDGE,
507*4882a593Smuzhiyun 	AXP22X_IRQ_GPIO1_INPUT,
508*4882a593Smuzhiyun 	AXP22X_IRQ_GPIO0_INPUT,
509*4882a593Smuzhiyun };
510*4882a593Smuzhiyun 
511*4882a593Smuzhiyun enum axp288_irqs {
512*4882a593Smuzhiyun 	AXP288_IRQ_VBUS_FALL     = 2,
513*4882a593Smuzhiyun 	AXP288_IRQ_VBUS_RISE,
514*4882a593Smuzhiyun 	AXP288_IRQ_OV,
515*4882a593Smuzhiyun 	AXP288_IRQ_FALLING_ALT,
516*4882a593Smuzhiyun 	AXP288_IRQ_RISING_ALT,
517*4882a593Smuzhiyun 	AXP288_IRQ_OV_ALT,
518*4882a593Smuzhiyun 	AXP288_IRQ_DONE          = 10,
519*4882a593Smuzhiyun 	AXP288_IRQ_CHARGING,
520*4882a593Smuzhiyun 	AXP288_IRQ_SAFE_QUIT,
521*4882a593Smuzhiyun 	AXP288_IRQ_SAFE_ENTER,
522*4882a593Smuzhiyun 	AXP288_IRQ_ABSENT,
523*4882a593Smuzhiyun 	AXP288_IRQ_APPEND,
524*4882a593Smuzhiyun 	AXP288_IRQ_QWBTU,
525*4882a593Smuzhiyun 	AXP288_IRQ_WBTU,
526*4882a593Smuzhiyun 	AXP288_IRQ_QWBTO,
527*4882a593Smuzhiyun 	AXP288_IRQ_WBTO,
528*4882a593Smuzhiyun 	AXP288_IRQ_QCBTU,
529*4882a593Smuzhiyun 	AXP288_IRQ_CBTU,
530*4882a593Smuzhiyun 	AXP288_IRQ_QCBTO,
531*4882a593Smuzhiyun 	AXP288_IRQ_CBTO,
532*4882a593Smuzhiyun 	AXP288_IRQ_WL2,
533*4882a593Smuzhiyun 	AXP288_IRQ_WL1,
534*4882a593Smuzhiyun 	AXP288_IRQ_GPADC,
535*4882a593Smuzhiyun 	AXP288_IRQ_OT            = 31,
536*4882a593Smuzhiyun 	AXP288_IRQ_GPIO0,
537*4882a593Smuzhiyun 	AXP288_IRQ_GPIO1,
538*4882a593Smuzhiyun 	AXP288_IRQ_POKO,
539*4882a593Smuzhiyun 	AXP288_IRQ_POKL,
540*4882a593Smuzhiyun 	AXP288_IRQ_POKS,
541*4882a593Smuzhiyun 	AXP288_IRQ_POKN,
542*4882a593Smuzhiyun 	AXP288_IRQ_POKP,
543*4882a593Smuzhiyun 	AXP288_IRQ_TIMER,
544*4882a593Smuzhiyun 	AXP288_IRQ_MV_CHNG,
545*4882a593Smuzhiyun 	AXP288_IRQ_BC_USB_CHNG,
546*4882a593Smuzhiyun };
547*4882a593Smuzhiyun 
548*4882a593Smuzhiyun enum axp803_irqs {
549*4882a593Smuzhiyun 	AXP803_IRQ_ACIN_OVER_V = 1,
550*4882a593Smuzhiyun 	AXP803_IRQ_ACIN_PLUGIN,
551*4882a593Smuzhiyun 	AXP803_IRQ_ACIN_REMOVAL,
552*4882a593Smuzhiyun 	AXP803_IRQ_VBUS_OVER_V,
553*4882a593Smuzhiyun 	AXP803_IRQ_VBUS_PLUGIN,
554*4882a593Smuzhiyun 	AXP803_IRQ_VBUS_REMOVAL,
555*4882a593Smuzhiyun 	AXP803_IRQ_BATT_PLUGIN,
556*4882a593Smuzhiyun 	AXP803_IRQ_BATT_REMOVAL,
557*4882a593Smuzhiyun 	AXP803_IRQ_BATT_ENT_ACT_MODE,
558*4882a593Smuzhiyun 	AXP803_IRQ_BATT_EXIT_ACT_MODE,
559*4882a593Smuzhiyun 	AXP803_IRQ_CHARG,
560*4882a593Smuzhiyun 	AXP803_IRQ_CHARG_DONE,
561*4882a593Smuzhiyun 	AXP803_IRQ_BATT_CHG_TEMP_HIGH,
562*4882a593Smuzhiyun 	AXP803_IRQ_BATT_CHG_TEMP_HIGH_END,
563*4882a593Smuzhiyun 	AXP803_IRQ_BATT_CHG_TEMP_LOW,
564*4882a593Smuzhiyun 	AXP803_IRQ_BATT_CHG_TEMP_LOW_END,
565*4882a593Smuzhiyun 	AXP803_IRQ_BATT_ACT_TEMP_HIGH,
566*4882a593Smuzhiyun 	AXP803_IRQ_BATT_ACT_TEMP_HIGH_END,
567*4882a593Smuzhiyun 	AXP803_IRQ_BATT_ACT_TEMP_LOW,
568*4882a593Smuzhiyun 	AXP803_IRQ_BATT_ACT_TEMP_LOW_END,
569*4882a593Smuzhiyun 	AXP803_IRQ_DIE_TEMP_HIGH,
570*4882a593Smuzhiyun 	AXP803_IRQ_GPADC,
571*4882a593Smuzhiyun 	AXP803_IRQ_LOW_PWR_LVL1,
572*4882a593Smuzhiyun 	AXP803_IRQ_LOW_PWR_LVL2,
573*4882a593Smuzhiyun 	AXP803_IRQ_TIMER,
574*4882a593Smuzhiyun 	AXP803_IRQ_PEK_RIS_EDGE,
575*4882a593Smuzhiyun 	AXP803_IRQ_PEK_FAL_EDGE,
576*4882a593Smuzhiyun 	AXP803_IRQ_PEK_SHORT,
577*4882a593Smuzhiyun 	AXP803_IRQ_PEK_LONG,
578*4882a593Smuzhiyun 	AXP803_IRQ_PEK_OVER_OFF,
579*4882a593Smuzhiyun 	AXP803_IRQ_GPIO1_INPUT,
580*4882a593Smuzhiyun 	AXP803_IRQ_GPIO0_INPUT,
581*4882a593Smuzhiyun 	AXP803_IRQ_BC_USB_CHNG,
582*4882a593Smuzhiyun 	AXP803_IRQ_MV_CHNG,
583*4882a593Smuzhiyun };
584*4882a593Smuzhiyun 
585*4882a593Smuzhiyun enum axp806_irqs {
586*4882a593Smuzhiyun 	AXP806_IRQ_DIE_TEMP_HIGH_LV1,
587*4882a593Smuzhiyun 	AXP806_IRQ_DIE_TEMP_HIGH_LV2,
588*4882a593Smuzhiyun 	AXP806_IRQ_DCDCA_V_LOW,
589*4882a593Smuzhiyun 	AXP806_IRQ_DCDCB_V_LOW,
590*4882a593Smuzhiyun 	AXP806_IRQ_DCDCC_V_LOW,
591*4882a593Smuzhiyun 	AXP806_IRQ_DCDCD_V_LOW,
592*4882a593Smuzhiyun 	AXP806_IRQ_DCDCE_V_LOW,
593*4882a593Smuzhiyun 	AXP806_IRQ_POK_LONG,
594*4882a593Smuzhiyun 	AXP806_IRQ_POK_SHORT,
595*4882a593Smuzhiyun 	AXP806_IRQ_WAKEUP,
596*4882a593Smuzhiyun 	AXP806_IRQ_POK_FALL,
597*4882a593Smuzhiyun 	AXP806_IRQ_POK_RISE,
598*4882a593Smuzhiyun };
599*4882a593Smuzhiyun 
600*4882a593Smuzhiyun enum axp809_irqs {
601*4882a593Smuzhiyun 	AXP809_IRQ_ACIN_OVER_V = 1,
602*4882a593Smuzhiyun 	AXP809_IRQ_ACIN_PLUGIN,
603*4882a593Smuzhiyun 	AXP809_IRQ_ACIN_REMOVAL,
604*4882a593Smuzhiyun 	AXP809_IRQ_VBUS_OVER_V,
605*4882a593Smuzhiyun 	AXP809_IRQ_VBUS_PLUGIN,
606*4882a593Smuzhiyun 	AXP809_IRQ_VBUS_REMOVAL,
607*4882a593Smuzhiyun 	AXP809_IRQ_VBUS_V_LOW,
608*4882a593Smuzhiyun 	AXP809_IRQ_BATT_PLUGIN,
609*4882a593Smuzhiyun 	AXP809_IRQ_BATT_REMOVAL,
610*4882a593Smuzhiyun 	AXP809_IRQ_BATT_ENT_ACT_MODE,
611*4882a593Smuzhiyun 	AXP809_IRQ_BATT_EXIT_ACT_MODE,
612*4882a593Smuzhiyun 	AXP809_IRQ_CHARG,
613*4882a593Smuzhiyun 	AXP809_IRQ_CHARG_DONE,
614*4882a593Smuzhiyun 	AXP809_IRQ_BATT_CHG_TEMP_HIGH,
615*4882a593Smuzhiyun 	AXP809_IRQ_BATT_CHG_TEMP_HIGH_END,
616*4882a593Smuzhiyun 	AXP809_IRQ_BATT_CHG_TEMP_LOW,
617*4882a593Smuzhiyun 	AXP809_IRQ_BATT_CHG_TEMP_LOW_END,
618*4882a593Smuzhiyun 	AXP809_IRQ_BATT_ACT_TEMP_HIGH,
619*4882a593Smuzhiyun 	AXP809_IRQ_BATT_ACT_TEMP_HIGH_END,
620*4882a593Smuzhiyun 	AXP809_IRQ_BATT_ACT_TEMP_LOW,
621*4882a593Smuzhiyun 	AXP809_IRQ_BATT_ACT_TEMP_LOW_END,
622*4882a593Smuzhiyun 	AXP809_IRQ_DIE_TEMP_HIGH,
623*4882a593Smuzhiyun 	AXP809_IRQ_LOW_PWR_LVL1,
624*4882a593Smuzhiyun 	AXP809_IRQ_LOW_PWR_LVL2,
625*4882a593Smuzhiyun 	AXP809_IRQ_TIMER,
626*4882a593Smuzhiyun 	AXP809_IRQ_PEK_RIS_EDGE,
627*4882a593Smuzhiyun 	AXP809_IRQ_PEK_FAL_EDGE,
628*4882a593Smuzhiyun 	AXP809_IRQ_PEK_SHORT,
629*4882a593Smuzhiyun 	AXP809_IRQ_PEK_LONG,
630*4882a593Smuzhiyun 	AXP809_IRQ_PEK_OVER_OFF,
631*4882a593Smuzhiyun 	AXP809_IRQ_GPIO1_INPUT,
632*4882a593Smuzhiyun 	AXP809_IRQ_GPIO0_INPUT,
633*4882a593Smuzhiyun };
634*4882a593Smuzhiyun 
635*4882a593Smuzhiyun struct axp20x_dev {
636*4882a593Smuzhiyun 	struct device			*dev;
637*4882a593Smuzhiyun 	int				irq;
638*4882a593Smuzhiyun 	unsigned long			irq_flags;
639*4882a593Smuzhiyun 	struct regmap			*regmap;
640*4882a593Smuzhiyun 	struct regmap_irq_chip_data	*regmap_irqc;
641*4882a593Smuzhiyun 	long				variant;
642*4882a593Smuzhiyun 	int                             nr_cells;
643*4882a593Smuzhiyun 	const struct mfd_cell           *cells;
644*4882a593Smuzhiyun 	const struct regmap_config	*regmap_cfg;
645*4882a593Smuzhiyun 	const struct regmap_irq_chip	*regmap_irq_chip;
646*4882a593Smuzhiyun };
647*4882a593Smuzhiyun 
648*4882a593Smuzhiyun /* generic helper function for reading 9-16 bit wide regs */
axp20x_read_variable_width(struct regmap * regmap,unsigned int reg,unsigned int width)649*4882a593Smuzhiyun static inline int axp20x_read_variable_width(struct regmap *regmap,
650*4882a593Smuzhiyun 	unsigned int reg, unsigned int width)
651*4882a593Smuzhiyun {
652*4882a593Smuzhiyun 	unsigned int reg_val, result;
653*4882a593Smuzhiyun 	int err;
654*4882a593Smuzhiyun 
655*4882a593Smuzhiyun 	err = regmap_read(regmap, reg, &reg_val);
656*4882a593Smuzhiyun 	if (err)
657*4882a593Smuzhiyun 		return err;
658*4882a593Smuzhiyun 
659*4882a593Smuzhiyun 	result = reg_val << (width - 8);
660*4882a593Smuzhiyun 
661*4882a593Smuzhiyun 	err = regmap_read(regmap, reg + 1, &reg_val);
662*4882a593Smuzhiyun 	if (err)
663*4882a593Smuzhiyun 		return err;
664*4882a593Smuzhiyun 
665*4882a593Smuzhiyun 	result |= reg_val;
666*4882a593Smuzhiyun 
667*4882a593Smuzhiyun 	return result;
668*4882a593Smuzhiyun }
669*4882a593Smuzhiyun 
670*4882a593Smuzhiyun /**
671*4882a593Smuzhiyun  * axp20x_match_device(): Setup axp20x variant related fields
672*4882a593Smuzhiyun  *
673*4882a593Smuzhiyun  * @axp20x: axp20x device to setup (.dev field must be set)
674*4882a593Smuzhiyun  * @dev: device associated with this axp20x device
675*4882a593Smuzhiyun  *
676*4882a593Smuzhiyun  * This lets the axp20x core configure the mfd cells and register maps
677*4882a593Smuzhiyun  * for later use.
678*4882a593Smuzhiyun  */
679*4882a593Smuzhiyun int axp20x_match_device(struct axp20x_dev *axp20x);
680*4882a593Smuzhiyun 
681*4882a593Smuzhiyun /**
682*4882a593Smuzhiyun  * axp20x_device_probe(): Probe a configured axp20x device
683*4882a593Smuzhiyun  *
684*4882a593Smuzhiyun  * @axp20x: axp20x device to probe (must be configured)
685*4882a593Smuzhiyun  *
686*4882a593Smuzhiyun  * This function lets the axp20x core register the axp20x mfd devices
687*4882a593Smuzhiyun  * and irqchip. The axp20x device passed in must be fully configured
688*4882a593Smuzhiyun  * with axp20x_match_device, its irq set, and regmap created.
689*4882a593Smuzhiyun  */
690*4882a593Smuzhiyun int axp20x_device_probe(struct axp20x_dev *axp20x);
691*4882a593Smuzhiyun 
692*4882a593Smuzhiyun /**
693*4882a593Smuzhiyun  * axp20x_device_remove(): Remove a axp20x device
694*4882a593Smuzhiyun  *
695*4882a593Smuzhiyun  * @axp20x: axp20x device to remove
696*4882a593Smuzhiyun  *
697*4882a593Smuzhiyun  * This tells the axp20x core to remove the associated mfd devices
698*4882a593Smuzhiyun  */
699*4882a593Smuzhiyun int axp20x_device_remove(struct axp20x_dev *axp20x);
700*4882a593Smuzhiyun 
701*4882a593Smuzhiyun #endif /* __LINUX_MFD_AXP20X_H */
702