1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * AS3711 PMIC MFC driver header 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2012 Renesas Electronics Corporation 6*4882a593Smuzhiyun * Author: Guennadi Liakhovetski, <g.liakhovetski@gmx.de> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef MFD_AS3711_H 10*4882a593Smuzhiyun #define MFD_AS3711_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Client data 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Register addresses */ 17*4882a593Smuzhiyun #define AS3711_SD_1_VOLTAGE 0 /* Digital Step-Down */ 18*4882a593Smuzhiyun #define AS3711_SD_2_VOLTAGE 1 19*4882a593Smuzhiyun #define AS3711_SD_3_VOLTAGE 2 20*4882a593Smuzhiyun #define AS3711_SD_4_VOLTAGE 3 21*4882a593Smuzhiyun #define AS3711_LDO_1_VOLTAGE 4 /* Analog LDO */ 22*4882a593Smuzhiyun #define AS3711_LDO_2_VOLTAGE 5 23*4882a593Smuzhiyun #define AS3711_LDO_3_VOLTAGE 6 /* Digital LDO */ 24*4882a593Smuzhiyun #define AS3711_LDO_4_VOLTAGE 7 25*4882a593Smuzhiyun #define AS3711_LDO_5_VOLTAGE 8 26*4882a593Smuzhiyun #define AS3711_LDO_6_VOLTAGE 9 27*4882a593Smuzhiyun #define AS3711_LDO_7_VOLTAGE 0xa 28*4882a593Smuzhiyun #define AS3711_LDO_8_VOLTAGE 0xb 29*4882a593Smuzhiyun #define AS3711_SD_CONTROL 0x10 30*4882a593Smuzhiyun #define AS3711_GPIO_SIGNAL_OUT 0x20 31*4882a593Smuzhiyun #define AS3711_GPIO_SIGNAL_IN 0x21 32*4882a593Smuzhiyun #define AS3711_SD_CONTROL_1 0x30 33*4882a593Smuzhiyun #define AS3711_SD_CONTROL_2 0x31 34*4882a593Smuzhiyun #define AS3711_CURR_CONTROL 0x40 35*4882a593Smuzhiyun #define AS3711_CURR1_VALUE 0x43 36*4882a593Smuzhiyun #define AS3711_CURR2_VALUE 0x44 37*4882a593Smuzhiyun #define AS3711_CURR3_VALUE 0x45 38*4882a593Smuzhiyun #define AS3711_STEPUP_CONTROL_1 0x50 39*4882a593Smuzhiyun #define AS3711_STEPUP_CONTROL_2 0x51 40*4882a593Smuzhiyun #define AS3711_STEPUP_CONTROL_4 0x53 41*4882a593Smuzhiyun #define AS3711_STEPUP_CONTROL_5 0x54 42*4882a593Smuzhiyun #define AS3711_REG_STATUS 0x73 43*4882a593Smuzhiyun #define AS3711_INTERRUPT_STATUS_1 0x77 44*4882a593Smuzhiyun #define AS3711_INTERRUPT_STATUS_2 0x78 45*4882a593Smuzhiyun #define AS3711_INTERRUPT_STATUS_3 0x79 46*4882a593Smuzhiyun #define AS3711_CHARGER_STATUS_1 0x86 47*4882a593Smuzhiyun #define AS3711_CHARGER_STATUS_2 0x87 48*4882a593Smuzhiyun #define AS3711_ASIC_ID_1 0x90 49*4882a593Smuzhiyun #define AS3711_ASIC_ID_2 0x91 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define AS3711_MAX_REG AS3711_ASIC_ID_2 52*4882a593Smuzhiyun #define AS3711_NUM_REGS (AS3711_MAX_REG + 1) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Regulators */ 55*4882a593Smuzhiyun enum { 56*4882a593Smuzhiyun AS3711_REGULATOR_SD_1, 57*4882a593Smuzhiyun AS3711_REGULATOR_SD_2, 58*4882a593Smuzhiyun AS3711_REGULATOR_SD_3, 59*4882a593Smuzhiyun AS3711_REGULATOR_SD_4, 60*4882a593Smuzhiyun AS3711_REGULATOR_LDO_1, 61*4882a593Smuzhiyun AS3711_REGULATOR_LDO_2, 62*4882a593Smuzhiyun AS3711_REGULATOR_LDO_3, 63*4882a593Smuzhiyun AS3711_REGULATOR_LDO_4, 64*4882a593Smuzhiyun AS3711_REGULATOR_LDO_5, 65*4882a593Smuzhiyun AS3711_REGULATOR_LDO_6, 66*4882a593Smuzhiyun AS3711_REGULATOR_LDO_7, 67*4882a593Smuzhiyun AS3711_REGULATOR_LDO_8, 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun AS3711_REGULATOR_MAX, 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun struct device; 73*4882a593Smuzhiyun struct regmap; 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct as3711 { 76*4882a593Smuzhiyun struct device *dev; 77*4882a593Smuzhiyun struct regmap *regmap; 78*4882a593Smuzhiyun }; 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define AS3711_MAX_STEPDOWN 4 81*4882a593Smuzhiyun #define AS3711_MAX_STEPUP 2 82*4882a593Smuzhiyun #define AS3711_MAX_LDO 8 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun enum as3711_su2_feedback { 85*4882a593Smuzhiyun AS3711_SU2_VOLTAGE, 86*4882a593Smuzhiyun AS3711_SU2_CURR1, 87*4882a593Smuzhiyun AS3711_SU2_CURR2, 88*4882a593Smuzhiyun AS3711_SU2_CURR3, 89*4882a593Smuzhiyun AS3711_SU2_CURR_AUTO, 90*4882a593Smuzhiyun }; 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun enum as3711_su2_fbprot { 93*4882a593Smuzhiyun AS3711_SU2_LX_SD4, 94*4882a593Smuzhiyun AS3711_SU2_GPIO2, 95*4882a593Smuzhiyun AS3711_SU2_GPIO3, 96*4882a593Smuzhiyun AS3711_SU2_GPIO4, 97*4882a593Smuzhiyun }; 98*4882a593Smuzhiyun 99*4882a593Smuzhiyun /* 100*4882a593Smuzhiyun * Platform data 101*4882a593Smuzhiyun */ 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun struct as3711_regulator_pdata { 104*4882a593Smuzhiyun struct regulator_init_data *init_data[AS3711_REGULATOR_MAX]; 105*4882a593Smuzhiyun }; 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun struct as3711_bl_pdata { 108*4882a593Smuzhiyun bool su1_fb; 109*4882a593Smuzhiyun int su1_max_uA; 110*4882a593Smuzhiyun bool su2_fb; 111*4882a593Smuzhiyun int su2_max_uA; 112*4882a593Smuzhiyun enum as3711_su2_feedback su2_feedback; 113*4882a593Smuzhiyun enum as3711_su2_fbprot su2_fbprot; 114*4882a593Smuzhiyun bool su2_auto_curr1; 115*4882a593Smuzhiyun bool su2_auto_curr2; 116*4882a593Smuzhiyun bool su2_auto_curr3; 117*4882a593Smuzhiyun }; 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun struct as3711_platform_data { 120*4882a593Smuzhiyun struct as3711_regulator_pdata regulator; 121*4882a593Smuzhiyun struct as3711_bl_pdata backlight; 122*4882a593Smuzhiyun }; 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #endif 125