xref: /OK3568_Linux_fs/kernel/include/linux/mfd/arizona/pdata.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Platform data for Arizona devices
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Copyright 2012 Wolfson Microelectronics. PLC.
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #ifndef _ARIZONA_PDATA_H
9*4882a593Smuzhiyun #define _ARIZONA_PDATA_H
10*4882a593Smuzhiyun 
11*4882a593Smuzhiyun #include <dt-bindings/mfd/arizona.h>
12*4882a593Smuzhiyun #include <linux/regulator/arizona-ldo1.h>
13*4882a593Smuzhiyun #include <linux/regulator/arizona-micsupp.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #define ARIZONA_GPN_DIR_MASK                     0x8000  /* GPN_DIR */
16*4882a593Smuzhiyun #define ARIZONA_GPN_DIR_SHIFT                        15  /* GPN_DIR */
17*4882a593Smuzhiyun #define ARIZONA_GPN_DIR_WIDTH                         1  /* GPN_DIR */
18*4882a593Smuzhiyun #define ARIZONA_GPN_PU_MASK                      0x4000  /* GPN_PU */
19*4882a593Smuzhiyun #define ARIZONA_GPN_PU_SHIFT                         14  /* GPN_PU */
20*4882a593Smuzhiyun #define ARIZONA_GPN_PU_WIDTH                          1  /* GPN_PU */
21*4882a593Smuzhiyun #define ARIZONA_GPN_PD_MASK                      0x2000  /* GPN_PD */
22*4882a593Smuzhiyun #define ARIZONA_GPN_PD_SHIFT                         13  /* GPN_PD */
23*4882a593Smuzhiyun #define ARIZONA_GPN_PD_WIDTH                          1  /* GPN_PD */
24*4882a593Smuzhiyun #define ARIZONA_GPN_LVL_MASK                     0x0800  /* GPN_LVL */
25*4882a593Smuzhiyun #define ARIZONA_GPN_LVL_SHIFT                        11  /* GPN_LVL */
26*4882a593Smuzhiyun #define ARIZONA_GPN_LVL_WIDTH                         1  /* GPN_LVL */
27*4882a593Smuzhiyun #define ARIZONA_GPN_POL_MASK                     0x0400  /* GPN_POL */
28*4882a593Smuzhiyun #define ARIZONA_GPN_POL_SHIFT                        10  /* GPN_POL */
29*4882a593Smuzhiyun #define ARIZONA_GPN_POL_WIDTH                         1  /* GPN_POL */
30*4882a593Smuzhiyun #define ARIZONA_GPN_OP_CFG_MASK                  0x0200  /* GPN_OP_CFG */
31*4882a593Smuzhiyun #define ARIZONA_GPN_OP_CFG_SHIFT                      9  /* GPN_OP_CFG */
32*4882a593Smuzhiyun #define ARIZONA_GPN_OP_CFG_WIDTH                      1  /* GPN_OP_CFG */
33*4882a593Smuzhiyun #define ARIZONA_GPN_DB_MASK                      0x0100  /* GPN_DB */
34*4882a593Smuzhiyun #define ARIZONA_GPN_DB_SHIFT                          8  /* GPN_DB */
35*4882a593Smuzhiyun #define ARIZONA_GPN_DB_WIDTH                          1  /* GPN_DB */
36*4882a593Smuzhiyun #define ARIZONA_GPN_FN_MASK                      0x007F  /* GPN_FN - [6:0] */
37*4882a593Smuzhiyun #define ARIZONA_GPN_FN_SHIFT                          0  /* GPN_FN - [6:0] */
38*4882a593Smuzhiyun #define ARIZONA_GPN_FN_WIDTH                          7  /* GPN_FN - [6:0] */
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun #define ARIZONA_MAX_GPIO 5
41*4882a593Smuzhiyun 
42*4882a593Smuzhiyun #define ARIZONA_MAX_INPUT 4
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun #define ARIZONA_MAX_MICBIAS 3
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun #define ARIZONA_MAX_OUTPUT 6
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define ARIZONA_MAX_AIF 3
49*4882a593Smuzhiyun 
50*4882a593Smuzhiyun #define ARIZONA_HAP_ACT_ERM 0
51*4882a593Smuzhiyun #define ARIZONA_HAP_ACT_LRA 2
52*4882a593Smuzhiyun 
53*4882a593Smuzhiyun #define ARIZONA_MAX_PDM_SPK 2
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun struct regulator_init_data;
56*4882a593Smuzhiyun struct gpio_desc;
57*4882a593Smuzhiyun 
58*4882a593Smuzhiyun struct arizona_micbias {
59*4882a593Smuzhiyun 	int mV;                    /** Regulated voltage */
60*4882a593Smuzhiyun 	unsigned int ext_cap:1;    /** External capacitor fitted */
61*4882a593Smuzhiyun 	unsigned int discharge:1;  /** Actively discharge */
62*4882a593Smuzhiyun 	unsigned int soft_start:1; /** Disable aggressive startup ramp rate */
63*4882a593Smuzhiyun 	unsigned int bypass:1;     /** Use bypass mode */
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun struct arizona_micd_config {
67*4882a593Smuzhiyun 	unsigned int src;
68*4882a593Smuzhiyun 	unsigned int bias;
69*4882a593Smuzhiyun 	bool gpio;
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun struct arizona_micd_range {
73*4882a593Smuzhiyun 	int max;  /** Ohms */
74*4882a593Smuzhiyun 	int key;  /** Key to report to input layer */
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun 
77*4882a593Smuzhiyun struct arizona_pdata {
78*4882a593Smuzhiyun 	struct gpio_desc *reset;      /** GPIO controlling /RESET, if any */
79*4882a593Smuzhiyun 
80*4882a593Smuzhiyun 	/** Regulator configuration for MICVDD */
81*4882a593Smuzhiyun 	struct arizona_micsupp_pdata micvdd;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	/** Regulator configuration for LDO1 */
84*4882a593Smuzhiyun 	struct arizona_ldo1_pdata ldo1;
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun 	/** If a direct 32kHz clock is provided on an MCLK specify it here */
87*4882a593Smuzhiyun 	int clk32k_src;
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun 	/** Mode for primary IRQ (defaults to active low) */
90*4882a593Smuzhiyun 	unsigned int irq_flags;
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	/* Base GPIO */
93*4882a593Smuzhiyun 	int gpio_base;
94*4882a593Smuzhiyun 
95*4882a593Smuzhiyun 	/** Pin state for GPIO pins */
96*4882a593Smuzhiyun 	unsigned int gpio_defaults[ARIZONA_MAX_GPIO];
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	/**
99*4882a593Smuzhiyun 	 * Maximum number of channels clocks will be generated for,
100*4882a593Smuzhiyun 	 * useful for systems where and I2S bus with multiple data
101*4882a593Smuzhiyun 	 * lines is mastered.
102*4882a593Smuzhiyun 	 */
103*4882a593Smuzhiyun 	unsigned int max_channels_clocked[ARIZONA_MAX_AIF];
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	/** GPIO5 is used for jack detection */
106*4882a593Smuzhiyun 	bool jd_gpio5;
107*4882a593Smuzhiyun 
108*4882a593Smuzhiyun 	/** Internal pull on GPIO5 is disabled when used for jack detection */
109*4882a593Smuzhiyun 	bool jd_gpio5_nopull;
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	/** set to true if jackdet contact opens on insert */
112*4882a593Smuzhiyun 	bool jd_invert;
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun 	/** Use the headphone detect circuit to identify the accessory */
115*4882a593Smuzhiyun 	bool hpdet_acc_id;
116*4882a593Smuzhiyun 
117*4882a593Smuzhiyun 	/** Check for line output with HPDET method */
118*4882a593Smuzhiyun 	bool hpdet_acc_id_line;
119*4882a593Smuzhiyun 
120*4882a593Smuzhiyun 	/** GPIO used for mic isolation with HPDET */
121*4882a593Smuzhiyun 	int hpdet_id_gpio;
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun 	/** Channel to use for headphone detection */
124*4882a593Smuzhiyun 	unsigned int hpdet_channel;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	/** Use software comparison to determine mic presence */
127*4882a593Smuzhiyun 	bool micd_software_compare;
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 	/** Extra debounce timeout used during initial mic detection (ms) */
130*4882a593Smuzhiyun 	unsigned int micd_detect_debounce;
131*4882a593Smuzhiyun 
132*4882a593Smuzhiyun 	/** GPIO for mic detection polarity */
133*4882a593Smuzhiyun 	int micd_pol_gpio;
134*4882a593Smuzhiyun 
135*4882a593Smuzhiyun 	/** Mic detect ramp rate */
136*4882a593Smuzhiyun 	unsigned int micd_bias_start_time;
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	/** Mic detect sample rate */
139*4882a593Smuzhiyun 	unsigned int micd_rate;
140*4882a593Smuzhiyun 
141*4882a593Smuzhiyun 	/** Mic detect debounce level */
142*4882a593Smuzhiyun 	unsigned int micd_dbtime;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	/** Mic detect timeout (ms) */
145*4882a593Smuzhiyun 	unsigned int micd_timeout;
146*4882a593Smuzhiyun 
147*4882a593Smuzhiyun 	/** Force MICBIAS on for mic detect */
148*4882a593Smuzhiyun 	bool micd_force_micbias;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	/** Mic detect level parameters */
151*4882a593Smuzhiyun 	const struct arizona_micd_range *micd_ranges;
152*4882a593Smuzhiyun 	int num_micd_ranges;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	/** Headset polarity configurations */
155*4882a593Smuzhiyun 	struct arizona_micd_config *micd_configs;
156*4882a593Smuzhiyun 	int num_micd_configs;
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/** Reference voltage for DMIC inputs */
159*4882a593Smuzhiyun 	int dmic_ref[ARIZONA_MAX_INPUT];
160*4882a593Smuzhiyun 
161*4882a593Smuzhiyun 	/** MICBIAS configurations */
162*4882a593Smuzhiyun 	struct arizona_micbias micbias[ARIZONA_MAX_MICBIAS];
163*4882a593Smuzhiyun 
164*4882a593Smuzhiyun 	/**
165*4882a593Smuzhiyun 	 * Mode of input structures
166*4882a593Smuzhiyun 	 * One of the ARIZONA_INMODE_xxx values
167*4882a593Smuzhiyun 	 * wm5102/wm5110/wm8280/wm8997: [0]=IN1 [1]=IN2 [2]=IN3 [3]=IN4
168*4882a593Smuzhiyun 	 * wm8998: [0]=IN1A [1]=IN2A [2]=IN1B [3]=IN2B
169*4882a593Smuzhiyun 	 */
170*4882a593Smuzhiyun 	int inmode[ARIZONA_MAX_INPUT];
171*4882a593Smuzhiyun 
172*4882a593Smuzhiyun 	/** Mode for outputs */
173*4882a593Smuzhiyun 	int out_mono[ARIZONA_MAX_OUTPUT];
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	/** Limit output volumes */
176*4882a593Smuzhiyun 	unsigned int out_vol_limit[2 * ARIZONA_MAX_OUTPUT];
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	/** PDM speaker mute setting */
179*4882a593Smuzhiyun 	unsigned int spk_mute[ARIZONA_MAX_PDM_SPK];
180*4882a593Smuzhiyun 
181*4882a593Smuzhiyun 	/** PDM speaker format */
182*4882a593Smuzhiyun 	unsigned int spk_fmt[ARIZONA_MAX_PDM_SPK];
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	/** Haptic actuator type */
185*4882a593Smuzhiyun 	unsigned int hap_act;
186*4882a593Smuzhiyun 
187*4882a593Smuzhiyun 	/** GPIO for primary IRQ (used for edge triggered emulation) */
188*4882a593Smuzhiyun 	int irq_gpio;
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun 	/** General purpose switch control */
191*4882a593Smuzhiyun 	unsigned int gpsw;
192*4882a593Smuzhiyun };
193*4882a593Smuzhiyun 
194*4882a593Smuzhiyun #endif
195