1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright Intel Corporation (C) 2014-2016. All Rights Reserved 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Declarations for Altera Arria10 MAX5 System Resource Chip 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Adapted from DA9052 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __MFD_ALTERA_A10SR_H 11*4882a593Smuzhiyun #define __MFD_ALTERA_A10SR_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/completion.h> 14*4882a593Smuzhiyun #include <linux/list.h> 15*4882a593Smuzhiyun #include <linux/mfd/core.h> 16*4882a593Smuzhiyun #include <linux/regmap.h> 17*4882a593Smuzhiyun #include <linux/slab.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Write registers are always on even addresses */ 20*4882a593Smuzhiyun #define WRITE_REG_MASK 0xFE 21*4882a593Smuzhiyun /* Odd registers are always on odd addresses */ 22*4882a593Smuzhiyun #define READ_REG_MASK 0x01 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define ALTR_A10SR_BITS_PER_REGISTER 8 25*4882a593Smuzhiyun /* 26*4882a593Smuzhiyun * To find the correct register, we divide the input GPIO by 27*4882a593Smuzhiyun * the number of GPIO in each register. We then need to multiply 28*4882a593Smuzhiyun * by 2 because the reads are at odd addresses. 29*4882a593Smuzhiyun */ 30*4882a593Smuzhiyun #define ALTR_A10SR_REG_OFFSET(X) (((X) / ALTR_A10SR_BITS_PER_REGISTER) << 1) 31*4882a593Smuzhiyun #define ALTR_A10SR_REG_BIT(X) ((X) % ALTR_A10SR_BITS_PER_REGISTER) 32*4882a593Smuzhiyun #define ALTR_A10SR_REG_BIT_CHG(X, Y) ((X) << ALTR_A10SR_REG_BIT(Y)) 33*4882a593Smuzhiyun #define ALTR_A10SR_REG_BIT_MASK(X) (1 << ALTR_A10SR_REG_BIT(X)) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* Arria10 System Controller Register Defines */ 36*4882a593Smuzhiyun #define ALTR_A10SR_NOP 0x00 /* No Change */ 37*4882a593Smuzhiyun #define ALTR_A10SR_VERSION_READ 0x00 /* MAX5 Version Read */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define ALTR_A10SR_LED_REG 0x02 /* LED - Upper 4 bits */ 40*4882a593Smuzhiyun /* LED register Bit Definitions */ 41*4882a593Smuzhiyun #define ALTR_A10SR_LED_VALID_SHIFT 4 /* LED - Upper 4 bits valid */ 42*4882a593Smuzhiyun #define ALTR_A10SR_OUT_VALID_RANGE_LO ALTR_A10SR_LED_VALID_SHIFT 43*4882a593Smuzhiyun #define ALTR_A10SR_OUT_VALID_RANGE_HI 7 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define ALTR_A10SR_PBDSW_REG 0x04 /* PB & DIP SW - Input only */ 46*4882a593Smuzhiyun #define ALTR_A10SR_PBDSW_IRQ_REG 0x06 /* PB & DIP SW Flag Clear */ 47*4882a593Smuzhiyun /* Pushbutton & DIP Switch Bit Definitions */ 48*4882a593Smuzhiyun #define ALTR_A10SR_IN_VALID_RANGE_LO 8 49*4882a593Smuzhiyun #define ALTR_A10SR_IN_VALID_RANGE_HI 15 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define ALTR_A10SR_PWR_GOOD1_REG 0x08 /* Power Good1 Read */ 52*4882a593Smuzhiyun #define ALTR_A10SR_PWR_GOOD2_REG 0x0A /* Power Good2 Read */ 53*4882a593Smuzhiyun #define ALTR_A10SR_PWR_GOOD3_REG 0x0C /* Power Good3 Read */ 54*4882a593Smuzhiyun #define ALTR_A10SR_FMCAB_REG 0x0E /* FMCA/B & PCIe Pwr Enable */ 55*4882a593Smuzhiyun #define ALTR_A10SR_HPS_RST_REG 0x10 /* HPS Reset */ 56*4882a593Smuzhiyun #define ALTR_A10SR_USB_QSPI_REG 0x12 /* USB, BQSPI, FILE Reset */ 57*4882a593Smuzhiyun #define ALTR_A10SR_SFPA_REG 0x14 /* SFPA Control Reg */ 58*4882a593Smuzhiyun #define ALTR_A10SR_SFPB_REG 0x16 /* SFPB Control Reg */ 59*4882a593Smuzhiyun #define ALTR_A10SR_I2C_M_REG 0x18 /* I2C Master Select */ 60*4882a593Smuzhiyun #define ALTR_A10SR_WARM_RST_REG 0x1A /* HPS Warm Reset */ 61*4882a593Smuzhiyun #define ALTR_A10SR_WR_KEY_REG 0x1C /* HPS Warm Reset Key */ 62*4882a593Smuzhiyun #define ALTR_A10SR_PMBUS_REG 0x1E /* HPS PM Bus */ 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /** 65*4882a593Smuzhiyun * struct altr_a10sr - Altera Max5 MFD device private data structure 66*4882a593Smuzhiyun * @dev: : this device 67*4882a593Smuzhiyun * @regmap: the regmap assigned to the parent device. 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun struct altr_a10sr { 70*4882a593Smuzhiyun struct device *dev; 71*4882a593Smuzhiyun struct regmap *regmap; 72*4882a593Smuzhiyun }; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun #endif /* __MFD_ALTERA_A10SR_H */ 75