1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Functions and registers to access AC100 codec / RTC combo IC. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Chen-Yu Tsai 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Chen-Yu Tsai <wens@csie.org> 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef __LINUX_MFD_AC100_H 11*4882a593Smuzhiyun #define __LINUX_MFD_AC100_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun #include <linux/regmap.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct ac100_dev { 16*4882a593Smuzhiyun struct device *dev; 17*4882a593Smuzhiyun struct regmap *regmap; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* Audio codec related registers */ 21*4882a593Smuzhiyun #define AC100_CHIP_AUDIO_RST 0x00 22*4882a593Smuzhiyun #define AC100_PLL_CTRL1 0x01 23*4882a593Smuzhiyun #define AC100_PLL_CTRL2 0x02 24*4882a593Smuzhiyun #define AC100_SYSCLK_CTRL 0x03 25*4882a593Smuzhiyun #define AC100_MOD_CLK_ENA 0x04 26*4882a593Smuzhiyun #define AC100_MOD_RST_CTRL 0x05 27*4882a593Smuzhiyun #define AC100_I2S_SR_CTRL 0x06 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* I2S1 interface */ 30*4882a593Smuzhiyun #define AC100_I2S1_CLK_CTRL 0x10 31*4882a593Smuzhiyun #define AC100_I2S1_SND_OUT_CTRL 0x11 32*4882a593Smuzhiyun #define AC100_I2S1_SND_IN_CTRL 0x12 33*4882a593Smuzhiyun #define AC100_I2S1_MXR_SRC 0x13 34*4882a593Smuzhiyun #define AC100_I2S1_VOL_CTRL1 0x14 35*4882a593Smuzhiyun #define AC100_I2S1_VOL_CTRL2 0x15 36*4882a593Smuzhiyun #define AC100_I2S1_VOL_CTRL3 0x16 37*4882a593Smuzhiyun #define AC100_I2S1_VOL_CTRL4 0x17 38*4882a593Smuzhiyun #define AC100_I2S1_MXR_GAIN 0x18 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* I2S2 interface */ 41*4882a593Smuzhiyun #define AC100_I2S2_CLK_CTRL 0x20 42*4882a593Smuzhiyun #define AC100_I2S2_SND_OUT_CTRL 0x21 43*4882a593Smuzhiyun #define AC100_I2S2_SND_IN_CTRL 0x22 44*4882a593Smuzhiyun #define AC100_I2S2_MXR_SRC 0x23 45*4882a593Smuzhiyun #define AC100_I2S2_VOL_CTRL1 0x24 46*4882a593Smuzhiyun #define AC100_I2S2_VOL_CTRL2 0x25 47*4882a593Smuzhiyun #define AC100_I2S2_VOL_CTRL3 0x26 48*4882a593Smuzhiyun #define AC100_I2S2_VOL_CTRL4 0x27 49*4882a593Smuzhiyun #define AC100_I2S2_MXR_GAIN 0x28 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* I2S3 interface */ 52*4882a593Smuzhiyun #define AC100_I2S3_CLK_CTRL 0x30 53*4882a593Smuzhiyun #define AC100_I2S3_SND_OUT_CTRL 0x31 54*4882a593Smuzhiyun #define AC100_I2S3_SND_IN_CTRL 0x32 55*4882a593Smuzhiyun #define AC100_I2S3_SIG_PATH_CTRL 0x33 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* ADC digital controls */ 58*4882a593Smuzhiyun #define AC100_ADC_DIG_CTRL 0x40 59*4882a593Smuzhiyun #define AC100_ADC_VOL_CTRL 0x41 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* HMIC plug sensing / key detection */ 62*4882a593Smuzhiyun #define AC100_HMIC_CTRL1 0x44 63*4882a593Smuzhiyun #define AC100_HMIC_CTRL2 0x45 64*4882a593Smuzhiyun #define AC100_HMIC_STATUS 0x46 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun /* DAC digital controls */ 67*4882a593Smuzhiyun #define AC100_DAC_DIG_CTRL 0x48 68*4882a593Smuzhiyun #define AC100_DAC_VOL_CTRL 0x49 69*4882a593Smuzhiyun #define AC100_DAC_MXR_SRC 0x4c 70*4882a593Smuzhiyun #define AC100_DAC_MXR_GAIN 0x4d 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* Analog controls */ 73*4882a593Smuzhiyun #define AC100_ADC_APC_CTRL 0x50 74*4882a593Smuzhiyun #define AC100_ADC_SRC 0x51 75*4882a593Smuzhiyun #define AC100_ADC_SRC_BST_CTRL 0x52 76*4882a593Smuzhiyun #define AC100_OUT_MXR_DAC_A_CTRL 0x53 77*4882a593Smuzhiyun #define AC100_OUT_MXR_SRC 0x54 78*4882a593Smuzhiyun #define AC100_OUT_MXR_SRC_BST 0x55 79*4882a593Smuzhiyun #define AC100_HPOUT_CTRL 0x56 80*4882a593Smuzhiyun #define AC100_ERPOUT_CTRL 0x57 81*4882a593Smuzhiyun #define AC100_SPKOUT_CTRL 0x58 82*4882a593Smuzhiyun #define AC100_LINEOUT_CTRL 0x59 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* ADC digital audio processing (high pass filter & auto gain control */ 85*4882a593Smuzhiyun #define AC100_ADC_DAP_L_STA 0x80 86*4882a593Smuzhiyun #define AC100_ADC_DAP_R_STA 0x81 87*4882a593Smuzhiyun #define AC100_ADC_DAP_L_CTRL 0x82 88*4882a593Smuzhiyun #define AC100_ADC_DAP_R_CTRL 0x83 89*4882a593Smuzhiyun #define AC100_ADC_DAP_L_T_L 0x84 /* Left Target Level */ 90*4882a593Smuzhiyun #define AC100_ADC_DAP_R_T_L 0x85 /* Right Target Level */ 91*4882a593Smuzhiyun #define AC100_ADC_DAP_L_H_A_C 0x86 /* Left High Avg. Coef */ 92*4882a593Smuzhiyun #define AC100_ADC_DAP_L_L_A_C 0x87 /* Left Low Avg. Coef */ 93*4882a593Smuzhiyun #define AC100_ADC_DAP_R_H_A_C 0x88 /* Right High Avg. Coef */ 94*4882a593Smuzhiyun #define AC100_ADC_DAP_R_L_A_C 0x89 /* Right Low Avg. Coef */ 95*4882a593Smuzhiyun #define AC100_ADC_DAP_L_D_T 0x8a /* Left Decay Time */ 96*4882a593Smuzhiyun #define AC100_ADC_DAP_L_A_T 0x8b /* Left Attack Time */ 97*4882a593Smuzhiyun #define AC100_ADC_DAP_R_D_T 0x8c /* Right Decay Time */ 98*4882a593Smuzhiyun #define AC100_ADC_DAP_R_A_T 0x8d /* Right Attack Time */ 99*4882a593Smuzhiyun #define AC100_ADC_DAP_N_TH 0x8e /* Noise Threshold */ 100*4882a593Smuzhiyun #define AC100_ADC_DAP_L_H_N_A_C 0x8f /* Left High Noise Avg. Coef */ 101*4882a593Smuzhiyun #define AC100_ADC_DAP_L_L_N_A_C 0x90 /* Left Low Noise Avg. Coef */ 102*4882a593Smuzhiyun #define AC100_ADC_DAP_R_H_N_A_C 0x91 /* Right High Noise Avg. Coef */ 103*4882a593Smuzhiyun #define AC100_ADC_DAP_R_L_N_A_C 0x92 /* Right Low Noise Avg. Coef */ 104*4882a593Smuzhiyun #define AC100_ADC_DAP_H_HPF_C 0x93 /* High High-Pass-Filter Coef */ 105*4882a593Smuzhiyun #define AC100_ADC_DAP_L_HPF_C 0x94 /* Low High-Pass-Filter Coef */ 106*4882a593Smuzhiyun #define AC100_ADC_DAP_OPT 0x95 /* AGC Optimum */ 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun /* DAC digital audio processing (high pass filter & dynamic range control) */ 109*4882a593Smuzhiyun #define AC100_DAC_DAP_CTRL 0xa0 110*4882a593Smuzhiyun #define AC100_DAC_DAP_H_HPF_C 0xa1 /* High High-Pass-Filter Coef */ 111*4882a593Smuzhiyun #define AC100_DAC_DAP_L_HPF_C 0xa2 /* Low High-Pass-Filter Coef */ 112*4882a593Smuzhiyun #define AC100_DAC_DAP_L_H_E_A_C 0xa3 /* Left High Energy Avg Coef */ 113*4882a593Smuzhiyun #define AC100_DAC_DAP_L_L_E_A_C 0xa4 /* Left Low Energy Avg Coef */ 114*4882a593Smuzhiyun #define AC100_DAC_DAP_R_H_E_A_C 0xa5 /* Right High Energy Avg Coef */ 115*4882a593Smuzhiyun #define AC100_DAC_DAP_R_L_E_A_C 0xa6 /* Right Low Energy Avg Coef */ 116*4882a593Smuzhiyun #define AC100_DAC_DAP_H_G_D_T_C 0xa7 /* High Gain Delay Time Coef */ 117*4882a593Smuzhiyun #define AC100_DAC_DAP_L_G_D_T_C 0xa8 /* Low Gain Delay Time Coef */ 118*4882a593Smuzhiyun #define AC100_DAC_DAP_H_G_A_T_C 0xa9 /* High Gain Attack Time Coef */ 119*4882a593Smuzhiyun #define AC100_DAC_DAP_L_G_A_T_C 0xaa /* Low Gain Attack Time Coef */ 120*4882a593Smuzhiyun #define AC100_DAC_DAP_H_E_TH 0xab /* High Energy Threshold */ 121*4882a593Smuzhiyun #define AC100_DAC_DAP_L_E_TH 0xac /* Low Energy Threshold */ 122*4882a593Smuzhiyun #define AC100_DAC_DAP_H_G_K 0xad /* High Gain K parameter */ 123*4882a593Smuzhiyun #define AC100_DAC_DAP_L_G_K 0xae /* Low Gain K parameter */ 124*4882a593Smuzhiyun #define AC100_DAC_DAP_H_G_OFF 0xaf /* High Gain offset */ 125*4882a593Smuzhiyun #define AC100_DAC_DAP_L_G_OFF 0xb0 /* Low Gain offset */ 126*4882a593Smuzhiyun #define AC100_DAC_DAP_OPT 0xb1 /* DRC optimum */ 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* Digital audio processing enable */ 129*4882a593Smuzhiyun #define AC100_ADC_DAP_ENA 0xb4 130*4882a593Smuzhiyun #define AC100_DAC_DAP_ENA 0xb5 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun /* SRC control */ 133*4882a593Smuzhiyun #define AC100_SRC1_CTRL1 0xb8 134*4882a593Smuzhiyun #define AC100_SRC1_CTRL2 0xb9 135*4882a593Smuzhiyun #define AC100_SRC1_CTRL3 0xba 136*4882a593Smuzhiyun #define AC100_SRC1_CTRL4 0xbb 137*4882a593Smuzhiyun #define AC100_SRC2_CTRL1 0xbc 138*4882a593Smuzhiyun #define AC100_SRC2_CTRL2 0xbd 139*4882a593Smuzhiyun #define AC100_SRC2_CTRL3 0xbe 140*4882a593Smuzhiyun #define AC100_SRC2_CTRL4 0xbf 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun /* RTC clk control */ 143*4882a593Smuzhiyun #define AC100_CLK32K_ANALOG_CTRL 0xc0 144*4882a593Smuzhiyun #define AC100_CLKOUT_CTRL1 0xc1 145*4882a593Smuzhiyun #define AC100_CLKOUT_CTRL2 0xc2 146*4882a593Smuzhiyun #define AC100_CLKOUT_CTRL3 0xc3 147*4882a593Smuzhiyun 148*4882a593Smuzhiyun /* RTC module */ 149*4882a593Smuzhiyun #define AC100_RTC_RST 0xc6 150*4882a593Smuzhiyun #define AC100_RTC_CTRL 0xc7 151*4882a593Smuzhiyun #define AC100_RTC_SEC 0xc8 /* second */ 152*4882a593Smuzhiyun #define AC100_RTC_MIN 0xc9 /* minute */ 153*4882a593Smuzhiyun #define AC100_RTC_HOU 0xca /* hour */ 154*4882a593Smuzhiyun #define AC100_RTC_WEE 0xcb /* weekday */ 155*4882a593Smuzhiyun #define AC100_RTC_DAY 0xcc /* day */ 156*4882a593Smuzhiyun #define AC100_RTC_MON 0xcd /* month */ 157*4882a593Smuzhiyun #define AC100_RTC_YEA 0xce /* year */ 158*4882a593Smuzhiyun #define AC100_RTC_UPD 0xcf /* update trigger */ 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* RTC alarm */ 161*4882a593Smuzhiyun #define AC100_ALM_INT_ENA 0xd0 162*4882a593Smuzhiyun #define AC100_ALM_INT_STA 0xd1 163*4882a593Smuzhiyun #define AC100_ALM_SEC 0xd8 164*4882a593Smuzhiyun #define AC100_ALM_MIN 0xd9 165*4882a593Smuzhiyun #define AC100_ALM_HOU 0xda 166*4882a593Smuzhiyun #define AC100_ALM_WEE 0xdb 167*4882a593Smuzhiyun #define AC100_ALM_DAY 0xdc 168*4882a593Smuzhiyun #define AC100_ALM_MON 0xdd 169*4882a593Smuzhiyun #define AC100_ALM_YEA 0xde 170*4882a593Smuzhiyun #define AC100_ALM_UPD 0xdf 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun /* RTC general purpose register 0 ~ 15 */ 173*4882a593Smuzhiyun #define AC100_RTC_GP(x) (0xe0 + (x)) 174*4882a593Smuzhiyun 175*4882a593Smuzhiyun #endif /* __LINUX_MFD_AC100_H */ 176