1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Marvell 88PM860x Interface 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2009 Marvell International Ltd. 6*4882a593Smuzhiyun * Haojian Zhuang <haojian.zhuang@marvell.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __LINUX_MFD_88PM860X_H 10*4882a593Smuzhiyun #define __LINUX_MFD_88PM860X_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/interrupt.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define MFD_NAME_SIZE (40) 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun enum { 17*4882a593Smuzhiyun CHIP_INVALID = 0, 18*4882a593Smuzhiyun CHIP_PM8606, 19*4882a593Smuzhiyun CHIP_PM8607, 20*4882a593Smuzhiyun CHIP_MAX, 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun enum { 24*4882a593Smuzhiyun PM8606_ID_INVALID, 25*4882a593Smuzhiyun PM8606_ID_BACKLIGHT, 26*4882a593Smuzhiyun PM8606_ID_LED, 27*4882a593Smuzhiyun PM8606_ID_VIBRATOR, 28*4882a593Smuzhiyun PM8606_ID_TOUCH, 29*4882a593Smuzhiyun PM8606_ID_SOUND, 30*4882a593Smuzhiyun PM8606_ID_CHARGER, 31*4882a593Smuzhiyun PM8606_ID_MAX, 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* 8606 Registers */ 36*4882a593Smuzhiyun #define PM8606_DCM_BOOST (0x00) 37*4882a593Smuzhiyun #define PM8606_PWM (0x01) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define PM8607_MISC2 (0x42) 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun /* Power Up Log Register */ 42*4882a593Smuzhiyun #define PM8607_POWER_UP_LOG (0x3F) 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun /* Charger Control Registers */ 45*4882a593Smuzhiyun #define PM8607_CCNT (0x47) 46*4882a593Smuzhiyun #define PM8607_CHG_CTRL1 (0x48) 47*4882a593Smuzhiyun #define PM8607_CHG_CTRL2 (0x49) 48*4882a593Smuzhiyun #define PM8607_CHG_CTRL3 (0x4A) 49*4882a593Smuzhiyun #define PM8607_CHG_CTRL4 (0x4B) 50*4882a593Smuzhiyun #define PM8607_CHG_CTRL5 (0x4C) 51*4882a593Smuzhiyun #define PM8607_CHG_CTRL6 (0x4D) 52*4882a593Smuzhiyun #define PM8607_CHG_CTRL7 (0x4E) 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Backlight Registers */ 55*4882a593Smuzhiyun #define PM8606_WLED1A (0x02) 56*4882a593Smuzhiyun #define PM8606_WLED1B (0x03) 57*4882a593Smuzhiyun #define PM8606_WLED2A (0x04) 58*4882a593Smuzhiyun #define PM8606_WLED2B (0x05) 59*4882a593Smuzhiyun #define PM8606_WLED3A (0x06) 60*4882a593Smuzhiyun #define PM8606_WLED3B (0x07) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* LED Registers */ 63*4882a593Smuzhiyun #define PM8606_RGB2A (0x08) 64*4882a593Smuzhiyun #define PM8606_RGB2B (0x09) 65*4882a593Smuzhiyun #define PM8606_RGB2C (0x0A) 66*4882a593Smuzhiyun #define PM8606_RGB2D (0x0B) 67*4882a593Smuzhiyun #define PM8606_RGB1A (0x0C) 68*4882a593Smuzhiyun #define PM8606_RGB1B (0x0D) 69*4882a593Smuzhiyun #define PM8606_RGB1C (0x0E) 70*4882a593Smuzhiyun #define PM8606_RGB1D (0x0F) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun #define PM8606_PREREGULATORA (0x10) 73*4882a593Smuzhiyun #define PM8606_PREREGULATORB (0x11) 74*4882a593Smuzhiyun #define PM8606_VIBRATORA (0x12) 75*4882a593Smuzhiyun #define PM8606_VIBRATORB (0x13) 76*4882a593Smuzhiyun #define PM8606_VCHG (0x14) 77*4882a593Smuzhiyun #define PM8606_VSYS (0x15) 78*4882a593Smuzhiyun #define PM8606_MISC (0x16) 79*4882a593Smuzhiyun #define PM8606_CHIP_ID (0x17) 80*4882a593Smuzhiyun #define PM8606_STATUS (0x18) 81*4882a593Smuzhiyun #define PM8606_FLAGS (0x19) 82*4882a593Smuzhiyun #define PM8606_PROTECTA (0x1A) 83*4882a593Smuzhiyun #define PM8606_PROTECTB (0x1B) 84*4882a593Smuzhiyun #define PM8606_PROTECTC (0x1C) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun /* Bit definitions of PM8606 registers */ 87*4882a593Smuzhiyun #define PM8606_DCM_500MA (0x0) /* current limit */ 88*4882a593Smuzhiyun #define PM8606_DCM_750MA (0x1) 89*4882a593Smuzhiyun #define PM8606_DCM_1000MA (0x2) 90*4882a593Smuzhiyun #define PM8606_DCM_1250MA (0x3) 91*4882a593Smuzhiyun #define PM8606_DCM_250MV (0x0 << 2) 92*4882a593Smuzhiyun #define PM8606_DCM_300MV (0x1 << 2) 93*4882a593Smuzhiyun #define PM8606_DCM_350MV (0x2 << 2) 94*4882a593Smuzhiyun #define PM8606_DCM_400MV (0x3 << 2) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #define PM8606_PWM_31200HZ (0x0) 97*4882a593Smuzhiyun #define PM8606_PWM_15600HZ (0x1) 98*4882a593Smuzhiyun #define PM8606_PWM_7800HZ (0x2) 99*4882a593Smuzhiyun #define PM8606_PWM_3900HZ (0x3) 100*4882a593Smuzhiyun #define PM8606_PWM_1950HZ (0x4) 101*4882a593Smuzhiyun #define PM8606_PWM_976HZ (0x5) 102*4882a593Smuzhiyun #define PM8606_PWM_488HZ (0x6) 103*4882a593Smuzhiyun #define PM8606_PWM_244HZ (0x7) 104*4882a593Smuzhiyun #define PM8606_PWM_FREQ_MASK (0x7) 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun #define PM8606_WLED_ON (1 << 0) 107*4882a593Smuzhiyun #define PM8606_WLED_CURRENT(x) ((x & 0x1F) << 1) 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun #define PM8606_LED_CURRENT(x) (((x >> 2) & 0x07) << 5) 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #define PM8606_VSYS_EN (1 << 1) 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun #define PM8606_MISC_OSC_EN (1 << 4) 114*4882a593Smuzhiyun 115*4882a593Smuzhiyun enum { 116*4882a593Smuzhiyun PM8607_ID_BUCK1 = 0, 117*4882a593Smuzhiyun PM8607_ID_BUCK2, 118*4882a593Smuzhiyun PM8607_ID_BUCK3, 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun PM8607_ID_LDO1, 121*4882a593Smuzhiyun PM8607_ID_LDO2, 122*4882a593Smuzhiyun PM8607_ID_LDO3, 123*4882a593Smuzhiyun PM8607_ID_LDO4, 124*4882a593Smuzhiyun PM8607_ID_LDO5, 125*4882a593Smuzhiyun PM8607_ID_LDO6, 126*4882a593Smuzhiyun PM8607_ID_LDO7, 127*4882a593Smuzhiyun PM8607_ID_LDO8, 128*4882a593Smuzhiyun PM8607_ID_LDO9, 129*4882a593Smuzhiyun PM8607_ID_LDO10, 130*4882a593Smuzhiyun PM8607_ID_LDO11, 131*4882a593Smuzhiyun PM8607_ID_LDO12, 132*4882a593Smuzhiyun PM8607_ID_LDO13, 133*4882a593Smuzhiyun PM8607_ID_LDO14, 134*4882a593Smuzhiyun PM8607_ID_LDO15, 135*4882a593Smuzhiyun PM8606_ID_PREG, 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun PM8607_ID_RG_MAX, 138*4882a593Smuzhiyun }; 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* 8607 chip ID is 0x40 or 0x50 */ 141*4882a593Smuzhiyun #define PM8607_VERSION_MASK (0xF0) /* 8607 chip ID mask */ 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* Interrupt Registers */ 144*4882a593Smuzhiyun #define PM8607_STATUS_1 (0x01) 145*4882a593Smuzhiyun #define PM8607_STATUS_2 (0x02) 146*4882a593Smuzhiyun #define PM8607_INT_STATUS1 (0x03) 147*4882a593Smuzhiyun #define PM8607_INT_STATUS2 (0x04) 148*4882a593Smuzhiyun #define PM8607_INT_STATUS3 (0x05) 149*4882a593Smuzhiyun #define PM8607_INT_MASK_1 (0x06) 150*4882a593Smuzhiyun #define PM8607_INT_MASK_2 (0x07) 151*4882a593Smuzhiyun #define PM8607_INT_MASK_3 (0x08) 152*4882a593Smuzhiyun 153*4882a593Smuzhiyun /* Regulator Control Registers */ 154*4882a593Smuzhiyun #define PM8607_LDO1 (0x10) 155*4882a593Smuzhiyun #define PM8607_LDO2 (0x11) 156*4882a593Smuzhiyun #define PM8607_LDO3 (0x12) 157*4882a593Smuzhiyun #define PM8607_LDO4 (0x13) 158*4882a593Smuzhiyun #define PM8607_LDO5 (0x14) 159*4882a593Smuzhiyun #define PM8607_LDO6 (0x15) 160*4882a593Smuzhiyun #define PM8607_LDO7 (0x16) 161*4882a593Smuzhiyun #define PM8607_LDO8 (0x17) 162*4882a593Smuzhiyun #define PM8607_LDO9 (0x18) 163*4882a593Smuzhiyun #define PM8607_LDO10 (0x19) 164*4882a593Smuzhiyun #define PM8607_LDO12 (0x1A) 165*4882a593Smuzhiyun #define PM8607_LDO14 (0x1B) 166*4882a593Smuzhiyun #define PM8607_SLEEP_MODE1 (0x1C) 167*4882a593Smuzhiyun #define PM8607_SLEEP_MODE2 (0x1D) 168*4882a593Smuzhiyun #define PM8607_SLEEP_MODE3 (0x1E) 169*4882a593Smuzhiyun #define PM8607_SLEEP_MODE4 (0x1F) 170*4882a593Smuzhiyun #define PM8607_GO (0x20) 171*4882a593Smuzhiyun #define PM8607_SLEEP_BUCK1 (0x21) 172*4882a593Smuzhiyun #define PM8607_SLEEP_BUCK2 (0x22) 173*4882a593Smuzhiyun #define PM8607_SLEEP_BUCK3 (0x23) 174*4882a593Smuzhiyun #define PM8607_BUCK1 (0x24) 175*4882a593Smuzhiyun #define PM8607_BUCK2 (0x25) 176*4882a593Smuzhiyun #define PM8607_BUCK3 (0x26) 177*4882a593Smuzhiyun #define PM8607_BUCK_CONTROLS (0x27) 178*4882a593Smuzhiyun #define PM8607_SUPPLIES_EN11 (0x2B) 179*4882a593Smuzhiyun #define PM8607_SUPPLIES_EN12 (0x2C) 180*4882a593Smuzhiyun #define PM8607_GROUP1 (0x2D) 181*4882a593Smuzhiyun #define PM8607_GROUP2 (0x2E) 182*4882a593Smuzhiyun #define PM8607_GROUP3 (0x2F) 183*4882a593Smuzhiyun #define PM8607_GROUP4 (0x30) 184*4882a593Smuzhiyun #define PM8607_GROUP5 (0x31) 185*4882a593Smuzhiyun #define PM8607_GROUP6 (0x32) 186*4882a593Smuzhiyun #define PM8607_SUPPLIES_EN21 (0x33) 187*4882a593Smuzhiyun #define PM8607_SUPPLIES_EN22 (0x34) 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun /* Vibrator Control Registers */ 190*4882a593Smuzhiyun #define PM8607_VIBRATOR_SET (0x28) 191*4882a593Smuzhiyun #define PM8607_VIBRATOR_PWM (0x29) 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun /* GPADC Registers */ 194*4882a593Smuzhiyun #define PM8607_GP_BIAS1 (0x4F) 195*4882a593Smuzhiyun #define PM8607_MEAS_EN1 (0x50) 196*4882a593Smuzhiyun #define PM8607_MEAS_EN2 (0x51) 197*4882a593Smuzhiyun #define PM8607_MEAS_EN3 (0x52) 198*4882a593Smuzhiyun #define PM8607_MEAS_OFF_TIME1 (0x53) 199*4882a593Smuzhiyun #define PM8607_MEAS_OFF_TIME2 (0x54) 200*4882a593Smuzhiyun #define PM8607_TSI_PREBIAS (0x55) /* prebias time */ 201*4882a593Smuzhiyun #define PM8607_PD_PREBIAS (0x56) /* prebias time */ 202*4882a593Smuzhiyun #define PM8607_GPADC_MISC1 (0x57) 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun /* bit definitions of MEAS_EN1*/ 205*4882a593Smuzhiyun #define PM8607_MEAS_EN1_VBAT (1 << 0) 206*4882a593Smuzhiyun #define PM8607_MEAS_EN1_VCHG (1 << 1) 207*4882a593Smuzhiyun #define PM8607_MEAS_EN1_VSYS (1 << 2) 208*4882a593Smuzhiyun #define PM8607_MEAS_EN1_TINT (1 << 3) 209*4882a593Smuzhiyun #define PM8607_MEAS_EN1_RFTMP (1 << 4) 210*4882a593Smuzhiyun #define PM8607_MEAS_EN1_TBAT (1 << 5) 211*4882a593Smuzhiyun #define PM8607_MEAS_EN1_GPADC2 (1 << 6) 212*4882a593Smuzhiyun #define PM8607_MEAS_EN1_GPADC3 (1 << 7) 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun /* Battery Monitor Registers */ 215*4882a593Smuzhiyun #define PM8607_GP_BIAS2 (0x5A) 216*4882a593Smuzhiyun #define PM8607_VBAT_LOWTH (0x5B) 217*4882a593Smuzhiyun #define PM8607_VCHG_LOWTH (0x5C) 218*4882a593Smuzhiyun #define PM8607_VSYS_LOWTH (0x5D) 219*4882a593Smuzhiyun #define PM8607_TINT_LOWTH (0x5E) 220*4882a593Smuzhiyun #define PM8607_GPADC0_LOWTH (0x5F) 221*4882a593Smuzhiyun #define PM8607_GPADC1_LOWTH (0x60) 222*4882a593Smuzhiyun #define PM8607_GPADC2_LOWTH (0x61) 223*4882a593Smuzhiyun #define PM8607_GPADC3_LOWTH (0x62) 224*4882a593Smuzhiyun #define PM8607_VBAT_HIGHTH (0x63) 225*4882a593Smuzhiyun #define PM8607_VCHG_HIGHTH (0x64) 226*4882a593Smuzhiyun #define PM8607_VSYS_HIGHTH (0x65) 227*4882a593Smuzhiyun #define PM8607_TINT_HIGHTH (0x66) 228*4882a593Smuzhiyun #define PM8607_GPADC0_HIGHTH (0x67) 229*4882a593Smuzhiyun #define PM8607_GPADC1_HIGHTH (0x68) 230*4882a593Smuzhiyun #define PM8607_GPADC2_HIGHTH (0x69) 231*4882a593Smuzhiyun #define PM8607_GPADC3_HIGHTH (0x6A) 232*4882a593Smuzhiyun #define PM8607_IBAT_MEAS1 (0x6B) 233*4882a593Smuzhiyun #define PM8607_IBAT_MEAS2 (0x6C) 234*4882a593Smuzhiyun #define PM8607_VBAT_MEAS1 (0x6D) 235*4882a593Smuzhiyun #define PM8607_VBAT_MEAS2 (0x6E) 236*4882a593Smuzhiyun #define PM8607_VCHG_MEAS1 (0x6F) 237*4882a593Smuzhiyun #define PM8607_VCHG_MEAS2 (0x70) 238*4882a593Smuzhiyun #define PM8607_VSYS_MEAS1 (0x71) 239*4882a593Smuzhiyun #define PM8607_VSYS_MEAS2 (0x72) 240*4882a593Smuzhiyun #define PM8607_TINT_MEAS1 (0x73) 241*4882a593Smuzhiyun #define PM8607_TINT_MEAS2 (0x74) 242*4882a593Smuzhiyun #define PM8607_GPADC0_MEAS1 (0x75) 243*4882a593Smuzhiyun #define PM8607_GPADC0_MEAS2 (0x76) 244*4882a593Smuzhiyun #define PM8607_GPADC1_MEAS1 (0x77) 245*4882a593Smuzhiyun #define PM8607_GPADC1_MEAS2 (0x78) 246*4882a593Smuzhiyun #define PM8607_GPADC2_MEAS1 (0x79) 247*4882a593Smuzhiyun #define PM8607_GPADC2_MEAS2 (0x7A) 248*4882a593Smuzhiyun #define PM8607_GPADC3_MEAS1 (0x7B) 249*4882a593Smuzhiyun #define PM8607_GPADC3_MEAS2 (0x7C) 250*4882a593Smuzhiyun #define PM8607_CCNT_MEAS1 (0x95) 251*4882a593Smuzhiyun #define PM8607_CCNT_MEAS2 (0x96) 252*4882a593Smuzhiyun #define PM8607_VBAT_AVG (0x97) 253*4882a593Smuzhiyun #define PM8607_VCHG_AVG (0x98) 254*4882a593Smuzhiyun #define PM8607_VSYS_AVG (0x99) 255*4882a593Smuzhiyun #define PM8607_VBAT_MIN (0x9A) 256*4882a593Smuzhiyun #define PM8607_VCHG_MIN (0x9B) 257*4882a593Smuzhiyun #define PM8607_VSYS_MIN (0x9C) 258*4882a593Smuzhiyun #define PM8607_VBAT_MAX (0x9D) 259*4882a593Smuzhiyun #define PM8607_VCHG_MAX (0x9E) 260*4882a593Smuzhiyun #define PM8607_VSYS_MAX (0x9F) 261*4882a593Smuzhiyun 262*4882a593Smuzhiyun #define PM8607_GPADC_MISC2 (0x59) 263*4882a593Smuzhiyun #define PM8607_GPADC0_GP_BIAS_A0 (1 << 0) 264*4882a593Smuzhiyun #define PM8607_GPADC1_GP_BIAS_A1 (1 << 1) 265*4882a593Smuzhiyun #define PM8607_GPADC2_GP_BIAS_A2 (1 << 2) 266*4882a593Smuzhiyun #define PM8607_GPADC3_GP_BIAS_A3 (1 << 3) 267*4882a593Smuzhiyun #define PM8607_GPADC2_GP_BIAS_OUT2 (1 << 6) 268*4882a593Smuzhiyun 269*4882a593Smuzhiyun /* RTC Control Registers */ 270*4882a593Smuzhiyun #define PM8607_RTC1 (0xA0) 271*4882a593Smuzhiyun #define PM8607_RTC_COUNTER1 (0xA1) 272*4882a593Smuzhiyun #define PM8607_RTC_COUNTER2 (0xA2) 273*4882a593Smuzhiyun #define PM8607_RTC_COUNTER3 (0xA3) 274*4882a593Smuzhiyun #define PM8607_RTC_COUNTER4 (0xA4) 275*4882a593Smuzhiyun #define PM8607_RTC_EXPIRE1 (0xA5) 276*4882a593Smuzhiyun #define PM8607_RTC_EXPIRE2 (0xA6) 277*4882a593Smuzhiyun #define PM8607_RTC_EXPIRE3 (0xA7) 278*4882a593Smuzhiyun #define PM8607_RTC_EXPIRE4 (0xA8) 279*4882a593Smuzhiyun #define PM8607_RTC_TRIM1 (0xA9) 280*4882a593Smuzhiyun #define PM8607_RTC_TRIM2 (0xAA) 281*4882a593Smuzhiyun #define PM8607_RTC_TRIM3 (0xAB) 282*4882a593Smuzhiyun #define PM8607_RTC_TRIM4 (0xAC) 283*4882a593Smuzhiyun #define PM8607_RTC_MISC1 (0xAD) 284*4882a593Smuzhiyun #define PM8607_RTC_MISC2 (0xAE) 285*4882a593Smuzhiyun #define PM8607_RTC_MISC3 (0xAF) 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun /* Misc Registers */ 288*4882a593Smuzhiyun #define PM8607_CHIP_ID (0x00) 289*4882a593Smuzhiyun #define PM8607_B0_MISC1 (0x0C) 290*4882a593Smuzhiyun #define PM8607_LDO1 (0x10) 291*4882a593Smuzhiyun #define PM8607_DVC3 (0x26) 292*4882a593Smuzhiyun #define PM8607_A1_MISC1 (0x40) 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun /* bit definitions of Status Query Interface */ 295*4882a593Smuzhiyun #define PM8607_STATUS_CC (1 << 3) 296*4882a593Smuzhiyun #define PM8607_STATUS_PEN (1 << 4) 297*4882a593Smuzhiyun #define PM8607_STATUS_HEADSET (1 << 5) 298*4882a593Smuzhiyun #define PM8607_STATUS_HOOK (1 << 6) 299*4882a593Smuzhiyun #define PM8607_STATUS_MICIN (1 << 7) 300*4882a593Smuzhiyun #define PM8607_STATUS_ONKEY (1 << 8) 301*4882a593Smuzhiyun #define PM8607_STATUS_EXTON (1 << 9) 302*4882a593Smuzhiyun #define PM8607_STATUS_CHG (1 << 10) 303*4882a593Smuzhiyun #define PM8607_STATUS_BAT (1 << 11) 304*4882a593Smuzhiyun #define PM8607_STATUS_VBUS (1 << 12) 305*4882a593Smuzhiyun #define PM8607_STATUS_OV (1 << 13) 306*4882a593Smuzhiyun 307*4882a593Smuzhiyun /* bit definitions of BUCK3 */ 308*4882a593Smuzhiyun #define PM8607_BUCK3_DOUBLE (1 << 6) 309*4882a593Smuzhiyun 310*4882a593Smuzhiyun /* bit definitions of Misc1 */ 311*4882a593Smuzhiyun #define PM8607_A1_MISC1_PI2C (1 << 0) 312*4882a593Smuzhiyun #define PM8607_B0_MISC1_INV_INT (1 << 0) 313*4882a593Smuzhiyun #define PM8607_B0_MISC1_INT_CLEAR (1 << 1) 314*4882a593Smuzhiyun #define PM8607_B0_MISC1_INT_MASK (1 << 2) 315*4882a593Smuzhiyun #define PM8607_B0_MISC1_PI2C (1 << 3) 316*4882a593Smuzhiyun #define PM8607_B0_MISC1_RESET (1 << 6) 317*4882a593Smuzhiyun 318*4882a593Smuzhiyun /* bits definitions of GPADC */ 319*4882a593Smuzhiyun #define PM8607_GPADC_EN (1 << 0) 320*4882a593Smuzhiyun #define PM8607_GPADC_PREBIAS_MASK (3 << 1) 321*4882a593Smuzhiyun #define PM8607_GPADC_SLOT_CYCLE_MASK (3 << 3) /* slow mode */ 322*4882a593Smuzhiyun #define PM8607_GPADC_OFF_SCALE_MASK (3 << 5) /* GP sleep mode */ 323*4882a593Smuzhiyun #define PM8607_GPADC_SW_CAL_MASK (1 << 7) 324*4882a593Smuzhiyun 325*4882a593Smuzhiyun #define PM8607_PD_PREBIAS_MASK (0x1F << 0) 326*4882a593Smuzhiyun #define PM8607_PD_PRECHG_MASK (7 << 5) 327*4882a593Smuzhiyun 328*4882a593Smuzhiyun #define PM8606_REF_GP_OSC_OFF 0 329*4882a593Smuzhiyun #define PM8606_REF_GP_OSC_ON 1 330*4882a593Smuzhiyun #define PM8606_REF_GP_OSC_UNKNOWN 2 331*4882a593Smuzhiyun 332*4882a593Smuzhiyun /* Clients of reference group and 8MHz oscillator in 88PM8606 */ 333*4882a593Smuzhiyun enum pm8606_ref_gp_and_osc_clients { 334*4882a593Smuzhiyun REF_GP_NO_CLIENTS = 0, 335*4882a593Smuzhiyun WLED1_DUTY = (1<<0), /*PF 0x02.7:0*/ 336*4882a593Smuzhiyun WLED2_DUTY = (1<<1), /*PF 0x04.7:0*/ 337*4882a593Smuzhiyun WLED3_DUTY = (1<<2), /*PF 0x06.7:0*/ 338*4882a593Smuzhiyun RGB1_ENABLE = (1<<3), /*PF 0x07.1*/ 339*4882a593Smuzhiyun RGB2_ENABLE = (1<<4), /*PF 0x07.2*/ 340*4882a593Smuzhiyun LDO_VBR_EN = (1<<5), /*PF 0x12.0*/ 341*4882a593Smuzhiyun REF_GP_MAX_CLIENT = 0xFFFF 342*4882a593Smuzhiyun }; 343*4882a593Smuzhiyun 344*4882a593Smuzhiyun /* Interrupt Number in 88PM8607 */ 345*4882a593Smuzhiyun enum { 346*4882a593Smuzhiyun PM8607_IRQ_ONKEY, 347*4882a593Smuzhiyun PM8607_IRQ_EXTON, 348*4882a593Smuzhiyun PM8607_IRQ_CHG, 349*4882a593Smuzhiyun PM8607_IRQ_BAT, 350*4882a593Smuzhiyun PM8607_IRQ_RTC, 351*4882a593Smuzhiyun PM8607_IRQ_CC, 352*4882a593Smuzhiyun PM8607_IRQ_VBAT, 353*4882a593Smuzhiyun PM8607_IRQ_VCHG, 354*4882a593Smuzhiyun PM8607_IRQ_VSYS, 355*4882a593Smuzhiyun PM8607_IRQ_TINT, 356*4882a593Smuzhiyun PM8607_IRQ_GPADC0, 357*4882a593Smuzhiyun PM8607_IRQ_GPADC1, 358*4882a593Smuzhiyun PM8607_IRQ_GPADC2, 359*4882a593Smuzhiyun PM8607_IRQ_GPADC3, 360*4882a593Smuzhiyun PM8607_IRQ_AUDIO_SHORT, 361*4882a593Smuzhiyun PM8607_IRQ_PEN, 362*4882a593Smuzhiyun PM8607_IRQ_HEADSET, 363*4882a593Smuzhiyun PM8607_IRQ_HOOK, 364*4882a593Smuzhiyun PM8607_IRQ_MICIN, 365*4882a593Smuzhiyun PM8607_IRQ_CHG_FAIL, 366*4882a593Smuzhiyun PM8607_IRQ_CHG_DONE, 367*4882a593Smuzhiyun PM8607_IRQ_CHG_FAULT, 368*4882a593Smuzhiyun }; 369*4882a593Smuzhiyun 370*4882a593Smuzhiyun enum { 371*4882a593Smuzhiyun PM8607_CHIP_A0 = 0x40, 372*4882a593Smuzhiyun PM8607_CHIP_A1 = 0x41, 373*4882a593Smuzhiyun PM8607_CHIP_B0 = 0x48, 374*4882a593Smuzhiyun }; 375*4882a593Smuzhiyun 376*4882a593Smuzhiyun struct pm860x_chip { 377*4882a593Smuzhiyun struct device *dev; 378*4882a593Smuzhiyun struct mutex irq_lock; 379*4882a593Smuzhiyun struct mutex osc_lock; 380*4882a593Smuzhiyun struct i2c_client *client; 381*4882a593Smuzhiyun struct i2c_client *companion; /* companion chip client */ 382*4882a593Smuzhiyun struct regmap *regmap; 383*4882a593Smuzhiyun struct regmap *regmap_companion; 384*4882a593Smuzhiyun 385*4882a593Smuzhiyun int buck3_double; /* DVC ramp slope double */ 386*4882a593Smuzhiyun int companion_addr; 387*4882a593Smuzhiyun unsigned short osc_vote; 388*4882a593Smuzhiyun int id; 389*4882a593Smuzhiyun int irq_mode; 390*4882a593Smuzhiyun int irq_base; 391*4882a593Smuzhiyun int core_irq; 392*4882a593Smuzhiyun unsigned char chip_version; 393*4882a593Smuzhiyun unsigned char osc_status; 394*4882a593Smuzhiyun 395*4882a593Smuzhiyun unsigned int wakeup_flag; 396*4882a593Smuzhiyun }; 397*4882a593Smuzhiyun 398*4882a593Smuzhiyun enum { 399*4882a593Smuzhiyun GI2C_PORT = 0, 400*4882a593Smuzhiyun PI2C_PORT, 401*4882a593Smuzhiyun }; 402*4882a593Smuzhiyun 403*4882a593Smuzhiyun struct pm860x_backlight_pdata { 404*4882a593Smuzhiyun int pwm; 405*4882a593Smuzhiyun int iset; 406*4882a593Smuzhiyun }; 407*4882a593Smuzhiyun 408*4882a593Smuzhiyun struct pm860x_led_pdata { 409*4882a593Smuzhiyun int iset; 410*4882a593Smuzhiyun }; 411*4882a593Smuzhiyun 412*4882a593Smuzhiyun struct pm860x_rtc_pdata { 413*4882a593Smuzhiyun int (*sync)(unsigned int ticks); 414*4882a593Smuzhiyun int vrtc; 415*4882a593Smuzhiyun }; 416*4882a593Smuzhiyun 417*4882a593Smuzhiyun struct pm860x_touch_pdata { 418*4882a593Smuzhiyun int gpadc_prebias; 419*4882a593Smuzhiyun int slot_cycle; 420*4882a593Smuzhiyun int off_scale; 421*4882a593Smuzhiyun int sw_cal; 422*4882a593Smuzhiyun int tsi_prebias; /* time, slot */ 423*4882a593Smuzhiyun int pen_prebias; /* time, slot */ 424*4882a593Smuzhiyun int pen_prechg; /* time, slot */ 425*4882a593Smuzhiyun int res_x; /* resistor of Xplate */ 426*4882a593Smuzhiyun unsigned long flags; 427*4882a593Smuzhiyun }; 428*4882a593Smuzhiyun 429*4882a593Smuzhiyun struct pm860x_power_pdata { 430*4882a593Smuzhiyun int max_capacity; 431*4882a593Smuzhiyun int resistor; 432*4882a593Smuzhiyun }; 433*4882a593Smuzhiyun 434*4882a593Smuzhiyun struct pm860x_platform_data { 435*4882a593Smuzhiyun struct pm860x_backlight_pdata *backlight; 436*4882a593Smuzhiyun struct pm860x_led_pdata *led; 437*4882a593Smuzhiyun struct pm860x_rtc_pdata *rtc; 438*4882a593Smuzhiyun struct pm860x_touch_pdata *touch; 439*4882a593Smuzhiyun struct pm860x_power_pdata *power; 440*4882a593Smuzhiyun struct regulator_init_data *buck1; 441*4882a593Smuzhiyun struct regulator_init_data *buck2; 442*4882a593Smuzhiyun struct regulator_init_data *buck3; 443*4882a593Smuzhiyun struct regulator_init_data *ldo1; 444*4882a593Smuzhiyun struct regulator_init_data *ldo2; 445*4882a593Smuzhiyun struct regulator_init_data *ldo3; 446*4882a593Smuzhiyun struct regulator_init_data *ldo4; 447*4882a593Smuzhiyun struct regulator_init_data *ldo5; 448*4882a593Smuzhiyun struct regulator_init_data *ldo6; 449*4882a593Smuzhiyun struct regulator_init_data *ldo7; 450*4882a593Smuzhiyun struct regulator_init_data *ldo8; 451*4882a593Smuzhiyun struct regulator_init_data *ldo9; 452*4882a593Smuzhiyun struct regulator_init_data *ldo10; 453*4882a593Smuzhiyun struct regulator_init_data *ldo12; 454*4882a593Smuzhiyun struct regulator_init_data *ldo_vibrator; 455*4882a593Smuzhiyun struct regulator_init_data *ldo14; 456*4882a593Smuzhiyun struct charger_desc *chg_desc; 457*4882a593Smuzhiyun 458*4882a593Smuzhiyun int companion_addr; /* I2C address of companion chip */ 459*4882a593Smuzhiyun int i2c_port; /* Controlled by GI2C or PI2C */ 460*4882a593Smuzhiyun int irq_mode; /* Clear interrupt by read/write(0/1) */ 461*4882a593Smuzhiyun int irq_base; /* IRQ base number of 88pm860x */ 462*4882a593Smuzhiyun int num_leds; 463*4882a593Smuzhiyun int num_backlights; 464*4882a593Smuzhiyun }; 465*4882a593Smuzhiyun 466*4882a593Smuzhiyun extern int pm8606_osc_enable(struct pm860x_chip *, unsigned short); 467*4882a593Smuzhiyun extern int pm8606_osc_disable(struct pm860x_chip *, unsigned short); 468*4882a593Smuzhiyun 469*4882a593Smuzhiyun extern int pm860x_reg_read(struct i2c_client *, int); 470*4882a593Smuzhiyun extern int pm860x_reg_write(struct i2c_client *, int, unsigned char); 471*4882a593Smuzhiyun extern int pm860x_bulk_read(struct i2c_client *, int, int, unsigned char *); 472*4882a593Smuzhiyun extern int pm860x_bulk_write(struct i2c_client *, int, int, unsigned char *); 473*4882a593Smuzhiyun extern int pm860x_set_bits(struct i2c_client *, int, unsigned char, 474*4882a593Smuzhiyun unsigned char); 475*4882a593Smuzhiyun extern int pm860x_page_reg_read(struct i2c_client *, int); 476*4882a593Smuzhiyun extern int pm860x_page_reg_write(struct i2c_client *, int, unsigned char); 477*4882a593Smuzhiyun extern int pm860x_page_bulk_read(struct i2c_client *, int, int, 478*4882a593Smuzhiyun unsigned char *); 479*4882a593Smuzhiyun extern int pm860x_page_bulk_write(struct i2c_client *, int, int, 480*4882a593Smuzhiyun unsigned char *); 481*4882a593Smuzhiyun extern int pm860x_page_set_bits(struct i2c_client *, int, unsigned char, 482*4882a593Smuzhiyun unsigned char); 483*4882a593Smuzhiyun 484*4882a593Smuzhiyun #endif /* __LINUX_MFD_88PM860X_H */ 485