1*4882a593Smuzhiyun /* mc146818rtc.h - register definitions for the Real-Time-Clock / CMOS RAM 2*4882a593Smuzhiyun * Copyright Torsten Duwe <duwe@informatik.uni-erlangen.de> 1993 3*4882a593Smuzhiyun * derived from Data Sheet, Copyright Motorola 1984 (!). 4*4882a593Smuzhiyun * It was written to be part of the Linux operating system. 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun /* permission is hereby granted to copy, modify and redistribute this code 7*4882a593Smuzhiyun * in terms of the GNU Library General Public License, Version 2 or later, 8*4882a593Smuzhiyun * at your option. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef _MC146818RTC_H 12*4882a593Smuzhiyun #define _MC146818RTC_H 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #include <asm/io.h> 15*4882a593Smuzhiyun #include <linux/rtc.h> /* get the user-level API */ 16*4882a593Smuzhiyun #include <asm/mc146818rtc.h> /* register access macros */ 17*4882a593Smuzhiyun #include <linux/bcd.h> 18*4882a593Smuzhiyun #include <linux/delay.h> 19*4882a593Smuzhiyun #include <linux/pm-trace.h> 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #ifdef __KERNEL__ 22*4882a593Smuzhiyun #include <linux/spinlock.h> /* spinlock_t */ 23*4882a593Smuzhiyun extern spinlock_t rtc_lock; /* serialize CMOS RAM access */ 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Some RTCs extend the mc146818 register set to support alarms of more 26*4882a593Smuzhiyun * than 24 hours in the future; or dates that include a century code. 27*4882a593Smuzhiyun * This platform_data structure can pass this information to the driver. 28*4882a593Smuzhiyun * 29*4882a593Smuzhiyun * Also, some platforms need suspend()/resume() hooks to kick in special 30*4882a593Smuzhiyun * handling of wake alarms, e.g. activating ACPI BIOS hooks or setting up 31*4882a593Smuzhiyun * a separate wakeup alarm used by some almost-clone chips. 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun struct cmos_rtc_board_info { 34*4882a593Smuzhiyun void (*wake_on)(struct device *dev); 35*4882a593Smuzhiyun void (*wake_off)(struct device *dev); 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun u32 flags; 38*4882a593Smuzhiyun #define CMOS_RTC_FLAGS_NOFREQ (1 << 0) 39*4882a593Smuzhiyun int address_space; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun u8 rtc_day_alarm; /* zero, or register index */ 42*4882a593Smuzhiyun u8 rtc_mon_alarm; /* zero, or register index */ 43*4882a593Smuzhiyun u8 rtc_century; /* zero, or register index */ 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun #endif 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun /********************************************************************** 48*4882a593Smuzhiyun * register summary 49*4882a593Smuzhiyun **********************************************************************/ 50*4882a593Smuzhiyun #define RTC_SECONDS 0 51*4882a593Smuzhiyun #define RTC_SECONDS_ALARM 1 52*4882a593Smuzhiyun #define RTC_MINUTES 2 53*4882a593Smuzhiyun #define RTC_MINUTES_ALARM 3 54*4882a593Smuzhiyun #define RTC_HOURS 4 55*4882a593Smuzhiyun #define RTC_HOURS_ALARM 5 56*4882a593Smuzhiyun /* RTC_*_alarm is always true if 2 MSBs are set */ 57*4882a593Smuzhiyun # define RTC_ALARM_DONT_CARE 0xC0 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define RTC_DAY_OF_WEEK 6 60*4882a593Smuzhiyun #define RTC_DAY_OF_MONTH 7 61*4882a593Smuzhiyun #define RTC_MONTH 8 62*4882a593Smuzhiyun #define RTC_YEAR 9 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* control registers - Moto names 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun #define RTC_REG_A 10 67*4882a593Smuzhiyun #define RTC_REG_B 11 68*4882a593Smuzhiyun #define RTC_REG_C 12 69*4882a593Smuzhiyun #define RTC_REG_D 13 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /********************************************************************** 72*4882a593Smuzhiyun * register details 73*4882a593Smuzhiyun **********************************************************************/ 74*4882a593Smuzhiyun #define RTC_FREQ_SELECT RTC_REG_A 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* update-in-progress - set to "1" 244 microsecs before RTC goes off the bus, 77*4882a593Smuzhiyun * reset after update (may take 1.984ms @ 32768Hz RefClock) is complete, 78*4882a593Smuzhiyun * totalling to a max high interval of 2.228 ms. 79*4882a593Smuzhiyun */ 80*4882a593Smuzhiyun # define RTC_UIP 0x80 81*4882a593Smuzhiyun # define RTC_DIV_CTL 0x70 82*4882a593Smuzhiyun /* divider control: refclock values 4.194 / 1.049 MHz / 32.768 kHz */ 83*4882a593Smuzhiyun # define RTC_REF_CLCK_4MHZ 0x00 84*4882a593Smuzhiyun # define RTC_REF_CLCK_1MHZ 0x10 85*4882a593Smuzhiyun # define RTC_REF_CLCK_32KHZ 0x20 86*4882a593Smuzhiyun /* 2 values for divider stage reset, others for "testing purposes only" */ 87*4882a593Smuzhiyun # define RTC_DIV_RESET1 0x60 88*4882a593Smuzhiyun # define RTC_DIV_RESET2 0x70 89*4882a593Smuzhiyun /* In AMD BKDG bit 5 and 6 are reserved, bit 4 is for select dv0 bank */ 90*4882a593Smuzhiyun # define RTC_AMD_BANK_SELECT 0x10 91*4882a593Smuzhiyun /* Periodic intr. / Square wave rate select. 0=none, 1=32.8kHz,... 15=2Hz */ 92*4882a593Smuzhiyun # define RTC_RATE_SELECT 0x0F 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /**********************************************************************/ 95*4882a593Smuzhiyun #define RTC_CONTROL RTC_REG_B 96*4882a593Smuzhiyun # define RTC_SET 0x80 /* disable updates for clock setting */ 97*4882a593Smuzhiyun # define RTC_PIE 0x40 /* periodic interrupt enable */ 98*4882a593Smuzhiyun # define RTC_AIE 0x20 /* alarm interrupt enable */ 99*4882a593Smuzhiyun # define RTC_UIE 0x10 /* update-finished interrupt enable */ 100*4882a593Smuzhiyun # define RTC_SQWE 0x08 /* enable square-wave output */ 101*4882a593Smuzhiyun # define RTC_DM_BINARY 0x04 /* all time/date values are BCD if clear */ 102*4882a593Smuzhiyun # define RTC_24H 0x02 /* 24 hour mode - else hours bit 7 means pm */ 103*4882a593Smuzhiyun # define RTC_DST_EN 0x01 /* auto switch DST - works f. USA only */ 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun /**********************************************************************/ 106*4882a593Smuzhiyun #define RTC_INTR_FLAGS RTC_REG_C 107*4882a593Smuzhiyun /* caution - cleared by read */ 108*4882a593Smuzhiyun # define RTC_IRQF 0x80 /* any of the following 3 is active */ 109*4882a593Smuzhiyun # define RTC_PF 0x40 110*4882a593Smuzhiyun # define RTC_AF 0x20 111*4882a593Smuzhiyun # define RTC_UF 0x10 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /**********************************************************************/ 114*4882a593Smuzhiyun #define RTC_VALID RTC_REG_D 115*4882a593Smuzhiyun # define RTC_VRT 0x80 /* valid RAM and time */ 116*4882a593Smuzhiyun /**********************************************************************/ 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #ifndef ARCH_RTC_LOCATION /* Override by <asm/mc146818rtc.h>? */ 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun #define RTC_IO_EXTENT 0x8 121*4882a593Smuzhiyun #define RTC_IO_EXTENT_USED 0x2 122*4882a593Smuzhiyun #define RTC_IOMAPPED 1 /* Default to I/O mapping. */ 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun #else 125*4882a593Smuzhiyun #define RTC_IO_EXTENT_USED RTC_IO_EXTENT 126*4882a593Smuzhiyun #endif /* ARCH_RTC_LOCATION */ 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun bool mc146818_does_rtc_work(void); 129*4882a593Smuzhiyun int mc146818_get_time(struct rtc_time *time); 130*4882a593Smuzhiyun int mc146818_set_time(struct rtc_time *time); 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun bool mc146818_avoid_UIP(void (*callback)(unsigned char seconds, void *param), 133*4882a593Smuzhiyun void *param); 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun #endif /* _MC146818RTC_H */ 136