1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Marvell MBUS common definitions.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Copyright (C) 2008 Marvell Semiconductor
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * This file is licensed under the terms of the GNU General Public
7*4882a593Smuzhiyun * License version 2. This program is licensed "as is" without any
8*4882a593Smuzhiyun * warranty of any kind, whether express or implied.
9*4882a593Smuzhiyun */
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #ifndef __LINUX_MBUS_H
12*4882a593Smuzhiyun #define __LINUX_MBUS_H
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/errno.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct resource;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun struct mbus_dram_target_info
19*4882a593Smuzhiyun {
20*4882a593Smuzhiyun /*
21*4882a593Smuzhiyun * The 4-bit MBUS target ID of the DRAM controller.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun u8 mbus_dram_target_id;
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /*
26*4882a593Smuzhiyun * The base address, size, and MBUS attribute ID for each
27*4882a593Smuzhiyun * of the possible DRAM chip selects. Peripherals are
28*4882a593Smuzhiyun * required to support at least 4 decode windows.
29*4882a593Smuzhiyun */
30*4882a593Smuzhiyun int num_cs;
31*4882a593Smuzhiyun struct mbus_dram_window {
32*4882a593Smuzhiyun u8 cs_index;
33*4882a593Smuzhiyun u8 mbus_attr;
34*4882a593Smuzhiyun u64 base;
35*4882a593Smuzhiyun u64 size;
36*4882a593Smuzhiyun } cs[4];
37*4882a593Smuzhiyun };
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun /* Flags for PCI/PCIe address decoding regions */
40*4882a593Smuzhiyun #define MVEBU_MBUS_PCI_IO 0x1
41*4882a593Smuzhiyun #define MVEBU_MBUS_PCI_MEM 0x2
42*4882a593Smuzhiyun #define MVEBU_MBUS_PCI_WA 0x3
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun * Magic value that explicits that we don't need a remapping-capable
46*4882a593Smuzhiyun * address decoding window.
47*4882a593Smuzhiyun */
48*4882a593Smuzhiyun #define MVEBU_MBUS_NO_REMAP (0xffffffff)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun /* Maximum size of a mbus window name */
51*4882a593Smuzhiyun #define MVEBU_MBUS_MAX_WINNAME_SZ 32
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun /*
54*4882a593Smuzhiyun * The Marvell mbus is to be found only on SOCs from the Orion family
55*4882a593Smuzhiyun * at the moment. Provide a dummy stub for other architectures.
56*4882a593Smuzhiyun */
57*4882a593Smuzhiyun #ifdef CONFIG_PLAT_ORION
58*4882a593Smuzhiyun extern const struct mbus_dram_target_info *mv_mbus_dram_info(void);
59*4882a593Smuzhiyun extern const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void);
60*4882a593Smuzhiyun int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size, u8 *target,
61*4882a593Smuzhiyun u8 *attr);
62*4882a593Smuzhiyun #else
mv_mbus_dram_info(void)63*4882a593Smuzhiyun static inline const struct mbus_dram_target_info *mv_mbus_dram_info(void)
64*4882a593Smuzhiyun {
65*4882a593Smuzhiyun return NULL;
66*4882a593Smuzhiyun }
mv_mbus_dram_info_nooverlap(void)67*4882a593Smuzhiyun static inline const struct mbus_dram_target_info *mv_mbus_dram_info_nooverlap(void)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun return NULL;
70*4882a593Smuzhiyun }
mvebu_mbus_get_io_win_info(phys_addr_t phyaddr,u32 * size,u8 * target,u8 * attr)71*4882a593Smuzhiyun static inline int mvebu_mbus_get_io_win_info(phys_addr_t phyaddr, u32 *size,
72*4882a593Smuzhiyun u8 *target, u8 *attr)
73*4882a593Smuzhiyun {
74*4882a593Smuzhiyun /*
75*4882a593Smuzhiyun * On all ARM32 MVEBU platforms with MBus support, this stub
76*4882a593Smuzhiyun * function will not get called. The real function from the
77*4882a593Smuzhiyun * MBus driver is called instead. ARM64 MVEBU platforms like
78*4882a593Smuzhiyun * the Armada 3700 could use the mv_xor device driver which calls
79*4882a593Smuzhiyun * into this function
80*4882a593Smuzhiyun */
81*4882a593Smuzhiyun return -EINVAL;
82*4882a593Smuzhiyun }
83*4882a593Smuzhiyun #endif
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun #ifdef CONFIG_MVEBU_MBUS
86*4882a593Smuzhiyun int mvebu_mbus_save_cpu_target(u32 __iomem *store_addr);
87*4882a593Smuzhiyun void mvebu_mbus_get_pcie_mem_aperture(struct resource *res);
88*4882a593Smuzhiyun void mvebu_mbus_get_pcie_io_aperture(struct resource *res);
89*4882a593Smuzhiyun int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target, u8 *attr);
90*4882a593Smuzhiyun int mvebu_mbus_add_window_remap_by_id(unsigned int target,
91*4882a593Smuzhiyun unsigned int attribute,
92*4882a593Smuzhiyun phys_addr_t base, size_t size,
93*4882a593Smuzhiyun phys_addr_t remap);
94*4882a593Smuzhiyun int mvebu_mbus_add_window_by_id(unsigned int target, unsigned int attribute,
95*4882a593Smuzhiyun phys_addr_t base, size_t size);
96*4882a593Smuzhiyun int mvebu_mbus_del_window(phys_addr_t base, size_t size);
97*4882a593Smuzhiyun int mvebu_mbus_init(const char *soc, phys_addr_t mbus_phys_base,
98*4882a593Smuzhiyun size_t mbus_size, phys_addr_t sdram_phys_base,
99*4882a593Smuzhiyun size_t sdram_size);
100*4882a593Smuzhiyun int mvebu_mbus_dt_init(bool is_coherent);
101*4882a593Smuzhiyun #else
mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr,u8 * target,u8 * attr)102*4882a593Smuzhiyun static inline int mvebu_mbus_get_dram_win_info(phys_addr_t phyaddr, u8 *target,
103*4882a593Smuzhiyun u8 *attr)
104*4882a593Smuzhiyun {
105*4882a593Smuzhiyun return -EINVAL;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun #endif /* CONFIG_MVEBU_MBUS */
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #endif /* __LINUX_MBUS_H */
110