1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2018 MediaTek Inc. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __MTK_CMDQ_MAILBOX_H__ 8*4882a593Smuzhiyun #define __MTK_CMDQ_MAILBOX_H__ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/platform_device.h> 11*4882a593Smuzhiyun #include <linux/slab.h> 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define CMDQ_INST_SIZE 8 /* instruction is 64-bit */ 15*4882a593Smuzhiyun #define CMDQ_SUBSYS_SHIFT 16 16*4882a593Smuzhiyun #define CMDQ_OP_CODE_SHIFT 24 17*4882a593Smuzhiyun #define CMDQ_JUMP_PASS CMDQ_INST_SIZE 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define CMDQ_WFE_UPDATE BIT(31) 20*4882a593Smuzhiyun #define CMDQ_WFE_UPDATE_VALUE BIT(16) 21*4882a593Smuzhiyun #define CMDQ_WFE_WAIT BIT(15) 22*4882a593Smuzhiyun #define CMDQ_WFE_WAIT_VALUE 0x1 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * WFE arg_b 26*4882a593Smuzhiyun * bit 0-11: wait value 27*4882a593Smuzhiyun * bit 15: 1 - wait, 0 - no wait 28*4882a593Smuzhiyun * bit 16-27: update value 29*4882a593Smuzhiyun * bit 31: 1 - update, 0 - no update 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #define CMDQ_WFE_OPTION (CMDQ_WFE_WAIT | CMDQ_WFE_WAIT_VALUE) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /** cmdq event maximum */ 34*4882a593Smuzhiyun #define CMDQ_MAX_EVENT 0x3ff 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun /* 37*4882a593Smuzhiyun * CMDQ_CODE_MASK: 38*4882a593Smuzhiyun * set write mask 39*4882a593Smuzhiyun * format: op mask 40*4882a593Smuzhiyun * CMDQ_CODE_WRITE: 41*4882a593Smuzhiyun * write value into target register 42*4882a593Smuzhiyun * format: op subsys address value 43*4882a593Smuzhiyun * CMDQ_CODE_JUMP: 44*4882a593Smuzhiyun * jump by offset 45*4882a593Smuzhiyun * format: op offset 46*4882a593Smuzhiyun * CMDQ_CODE_WFE: 47*4882a593Smuzhiyun * wait for event and clear 48*4882a593Smuzhiyun * it is just clear if no wait 49*4882a593Smuzhiyun * format: [wait] op event update:1 to_wait:1 wait:1 50*4882a593Smuzhiyun * [clear] op event update:1 to_wait:0 wait:0 51*4882a593Smuzhiyun * CMDQ_CODE_EOC: 52*4882a593Smuzhiyun * end of command 53*4882a593Smuzhiyun * format: op irq_flag 54*4882a593Smuzhiyun */ 55*4882a593Smuzhiyun enum cmdq_code { 56*4882a593Smuzhiyun CMDQ_CODE_MASK = 0x02, 57*4882a593Smuzhiyun CMDQ_CODE_WRITE = 0x04, 58*4882a593Smuzhiyun CMDQ_CODE_POLL = 0x08, 59*4882a593Smuzhiyun CMDQ_CODE_JUMP = 0x10, 60*4882a593Smuzhiyun CMDQ_CODE_WFE = 0x20, 61*4882a593Smuzhiyun CMDQ_CODE_EOC = 0x40, 62*4882a593Smuzhiyun CMDQ_CODE_READ_S = 0x80, 63*4882a593Smuzhiyun CMDQ_CODE_WRITE_S = 0x90, 64*4882a593Smuzhiyun CMDQ_CODE_WRITE_S_MASK = 0x91, 65*4882a593Smuzhiyun CMDQ_CODE_LOGIC = 0xa0, 66*4882a593Smuzhiyun }; 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun enum cmdq_cb_status { 69*4882a593Smuzhiyun CMDQ_CB_NORMAL = 0, 70*4882a593Smuzhiyun CMDQ_CB_ERROR 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun struct cmdq_cb_data { 74*4882a593Smuzhiyun enum cmdq_cb_status sta; 75*4882a593Smuzhiyun void *data; 76*4882a593Smuzhiyun }; 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun typedef void (*cmdq_async_flush_cb)(struct cmdq_cb_data data); 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun struct cmdq_task_cb { 81*4882a593Smuzhiyun cmdq_async_flush_cb cb; 82*4882a593Smuzhiyun void *data; 83*4882a593Smuzhiyun }; 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun struct cmdq_pkt { 86*4882a593Smuzhiyun void *va_base; 87*4882a593Smuzhiyun dma_addr_t pa_base; 88*4882a593Smuzhiyun size_t cmd_buf_size; /* command occupied size */ 89*4882a593Smuzhiyun size_t buf_size; /* real buffer size */ 90*4882a593Smuzhiyun struct cmdq_task_cb cb; 91*4882a593Smuzhiyun struct cmdq_task_cb async_cb; 92*4882a593Smuzhiyun void *cl; 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun u8 cmdq_get_shift_pa(struct mbox_chan *chan); 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #endif /* __MTK_CMDQ_MAILBOX_H__ */ 98