1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Author Karsten Keil <kkeil@novell.com> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Basic declarations for the mISDN HW channels 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Copyright 2008 by Karsten Keil <kkeil@novell.com> 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef MISDNHW_H 12*4882a593Smuzhiyun #define MISDNHW_H 13*4882a593Smuzhiyun #include <linux/mISDNif.h> 14*4882a593Smuzhiyun #include <linux/timer.h> 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* 17*4882a593Smuzhiyun * HW DEBUG 0xHHHHGGGG 18*4882a593Smuzhiyun * H - hardware driver specific bits 19*4882a593Smuzhiyun * G - for all drivers 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define DEBUG_HW 0x00000001 23*4882a593Smuzhiyun #define DEBUG_HW_OPEN 0x00000002 24*4882a593Smuzhiyun #define DEBUG_HW_DCHANNEL 0x00000100 25*4882a593Smuzhiyun #define DEBUG_HW_DFIFO 0x00000200 26*4882a593Smuzhiyun #define DEBUG_HW_BCHANNEL 0x00001000 27*4882a593Smuzhiyun #define DEBUG_HW_BFIFO 0x00002000 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #define MAX_DFRAME_LEN_L1 300 30*4882a593Smuzhiyun #define MAX_MON_FRAME 32 31*4882a593Smuzhiyun #define MAX_LOG_SPACE 2048 32*4882a593Smuzhiyun #define MISDN_COPY_SIZE 32 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* channel->Flags bit field */ 35*4882a593Smuzhiyun #define FLG_TX_BUSY 0 /* tx_buf in use */ 36*4882a593Smuzhiyun #define FLG_TX_NEXT 1 /* next_skb in use */ 37*4882a593Smuzhiyun #define FLG_L1_BUSY 2 /* L1 is permanent busy */ 38*4882a593Smuzhiyun #define FLG_L2_ACTIVATED 3 /* activated from L2 */ 39*4882a593Smuzhiyun #define FLG_OPEN 5 /* channel is in use */ 40*4882a593Smuzhiyun #define FLG_ACTIVE 6 /* channel is activated */ 41*4882a593Smuzhiyun #define FLG_BUSY_TIMER 7 42*4882a593Smuzhiyun /* channel type */ 43*4882a593Smuzhiyun #define FLG_DCHANNEL 8 /* channel is D-channel */ 44*4882a593Smuzhiyun #define FLG_BCHANNEL 9 /* channel is B-channel */ 45*4882a593Smuzhiyun #define FLG_ECHANNEL 10 /* channel is E-channel */ 46*4882a593Smuzhiyun #define FLG_TRANSPARENT 12 /* channel use transparent data */ 47*4882a593Smuzhiyun #define FLG_HDLC 13 /* channel use hdlc data */ 48*4882a593Smuzhiyun #define FLG_L2DATA 14 /* channel use L2 DATA primitivs */ 49*4882a593Smuzhiyun #define FLG_ORIGIN 15 /* channel is on origin site */ 50*4882a593Smuzhiyun /* channel specific stuff */ 51*4882a593Smuzhiyun #define FLG_FILLEMPTY 16 /* fill fifo on first frame (empty) */ 52*4882a593Smuzhiyun /* arcofi specific */ 53*4882a593Smuzhiyun #define FLG_ARCOFI_TIMER 17 54*4882a593Smuzhiyun #define FLG_ARCOFI_ERROR 18 55*4882a593Smuzhiyun /* isar specific */ 56*4882a593Smuzhiyun #define FLG_INITIALIZED 17 57*4882a593Smuzhiyun #define FLG_DLEETX 18 58*4882a593Smuzhiyun #define FLG_LASTDLE 19 59*4882a593Smuzhiyun #define FLG_FIRST 20 60*4882a593Smuzhiyun #define FLG_LASTDATA 21 61*4882a593Smuzhiyun #define FLG_NMD_DATA 22 62*4882a593Smuzhiyun #define FLG_FTI_RUN 23 63*4882a593Smuzhiyun #define FLG_LL_OK 24 64*4882a593Smuzhiyun #define FLG_LL_CONN 25 65*4882a593Smuzhiyun #define FLG_DTMFSEND 26 66*4882a593Smuzhiyun #define FLG_TX_EMPTY 27 67*4882a593Smuzhiyun /* stop sending received data upstream */ 68*4882a593Smuzhiyun #define FLG_RX_OFF 28 69*4882a593Smuzhiyun /* workq events */ 70*4882a593Smuzhiyun #define FLG_RECVQUEUE 30 71*4882a593Smuzhiyun #define FLG_PHCHANGE 31 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define schedule_event(s, ev) do { \ 74*4882a593Smuzhiyun test_and_set_bit(ev, &((s)->Flags)); \ 75*4882a593Smuzhiyun schedule_work(&((s)->workq)); \ 76*4882a593Smuzhiyun } while (0) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun struct dchannel { 79*4882a593Smuzhiyun struct mISDNdevice dev; 80*4882a593Smuzhiyun u_long Flags; 81*4882a593Smuzhiyun struct work_struct workq; 82*4882a593Smuzhiyun void (*phfunc) (struct dchannel *); 83*4882a593Smuzhiyun u_int state; 84*4882a593Smuzhiyun void *l1; 85*4882a593Smuzhiyun void *hw; 86*4882a593Smuzhiyun int slot; /* multiport card channel slot */ 87*4882a593Smuzhiyun struct timer_list timer; 88*4882a593Smuzhiyun /* receive data */ 89*4882a593Smuzhiyun struct sk_buff *rx_skb; 90*4882a593Smuzhiyun int maxlen; 91*4882a593Smuzhiyun /* send data */ 92*4882a593Smuzhiyun struct sk_buff_head squeue; 93*4882a593Smuzhiyun struct sk_buff_head rqueue; 94*4882a593Smuzhiyun struct sk_buff *tx_skb; 95*4882a593Smuzhiyun int tx_idx; 96*4882a593Smuzhiyun int debug; 97*4882a593Smuzhiyun /* statistics */ 98*4882a593Smuzhiyun int err_crc; 99*4882a593Smuzhiyun int err_tx; 100*4882a593Smuzhiyun int err_rx; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun 103*4882a593Smuzhiyun typedef int (dchannel_l1callback)(struct dchannel *, u_int); 104*4882a593Smuzhiyun extern int create_l1(struct dchannel *, dchannel_l1callback *); 105*4882a593Smuzhiyun 106*4882a593Smuzhiyun /* private L1 commands */ 107*4882a593Smuzhiyun #define INFO0 0x8002 108*4882a593Smuzhiyun #define INFO1 0x8102 109*4882a593Smuzhiyun #define INFO2 0x8202 110*4882a593Smuzhiyun #define INFO3_P8 0x8302 111*4882a593Smuzhiyun #define INFO3_P10 0x8402 112*4882a593Smuzhiyun #define INFO4_P8 0x8502 113*4882a593Smuzhiyun #define INFO4_P10 0x8602 114*4882a593Smuzhiyun #define LOSTFRAMING 0x8702 115*4882a593Smuzhiyun #define ANYSIGNAL 0x8802 116*4882a593Smuzhiyun #define HW_POWERDOWN 0x8902 117*4882a593Smuzhiyun #define HW_RESET_REQ 0x8a02 118*4882a593Smuzhiyun #define HW_POWERUP_REQ 0x8b02 119*4882a593Smuzhiyun #define HW_DEACT_REQ 0x8c02 120*4882a593Smuzhiyun #define HW_ACTIVATE_REQ 0x8e02 121*4882a593Smuzhiyun #define HW_D_NOBLOCKED 0x8f02 122*4882a593Smuzhiyun #define HW_RESET_IND 0x9002 123*4882a593Smuzhiyun #define HW_POWERUP_IND 0x9102 124*4882a593Smuzhiyun #define HW_DEACT_IND 0x9202 125*4882a593Smuzhiyun #define HW_ACTIVATE_IND 0x9302 126*4882a593Smuzhiyun #define HW_DEACT_CNF 0x9402 127*4882a593Smuzhiyun #define HW_TESTLOOP 0x9502 128*4882a593Smuzhiyun #define HW_TESTRX_RAW 0x9602 129*4882a593Smuzhiyun #define HW_TESTRX_HDLC 0x9702 130*4882a593Smuzhiyun #define HW_TESTRX_OFF 0x9802 131*4882a593Smuzhiyun #define HW_TIMER3_IND 0x9902 132*4882a593Smuzhiyun #define HW_TIMER3_VALUE 0x9a00 133*4882a593Smuzhiyun #define HW_TIMER3_VMASK 0x00FF 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun struct layer1; 136*4882a593Smuzhiyun extern int l1_event(struct layer1 *, u_int); 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun #define MISDN_BCH_FILL_SIZE 4 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun struct bchannel { 141*4882a593Smuzhiyun struct mISDNchannel ch; 142*4882a593Smuzhiyun int nr; 143*4882a593Smuzhiyun u_long Flags; 144*4882a593Smuzhiyun struct work_struct workq; 145*4882a593Smuzhiyun u_int state; 146*4882a593Smuzhiyun void *hw; 147*4882a593Smuzhiyun int slot; /* multiport card channel slot */ 148*4882a593Smuzhiyun struct timer_list timer; 149*4882a593Smuzhiyun /* receive data */ 150*4882a593Smuzhiyun u8 fill[MISDN_BCH_FILL_SIZE]; 151*4882a593Smuzhiyun struct sk_buff *rx_skb; 152*4882a593Smuzhiyun unsigned short maxlen; 153*4882a593Smuzhiyun unsigned short init_maxlen; /* initial value */ 154*4882a593Smuzhiyun unsigned short next_maxlen; /* pending value */ 155*4882a593Smuzhiyun unsigned short minlen; /* for transparent data */ 156*4882a593Smuzhiyun unsigned short init_minlen; /* initial value */ 157*4882a593Smuzhiyun unsigned short next_minlen; /* pending value */ 158*4882a593Smuzhiyun /* send data */ 159*4882a593Smuzhiyun struct sk_buff *next_skb; 160*4882a593Smuzhiyun struct sk_buff *tx_skb; 161*4882a593Smuzhiyun struct sk_buff_head rqueue; 162*4882a593Smuzhiyun int rcount; 163*4882a593Smuzhiyun int tx_idx; 164*4882a593Smuzhiyun int debug; 165*4882a593Smuzhiyun /* statistics */ 166*4882a593Smuzhiyun int err_crc; 167*4882a593Smuzhiyun int err_tx; 168*4882a593Smuzhiyun int err_rx; 169*4882a593Smuzhiyun int dropcnt; 170*4882a593Smuzhiyun }; 171*4882a593Smuzhiyun 172*4882a593Smuzhiyun extern int mISDN_initdchannel(struct dchannel *, int, void *); 173*4882a593Smuzhiyun extern int mISDN_initbchannel(struct bchannel *, unsigned short, 174*4882a593Smuzhiyun unsigned short); 175*4882a593Smuzhiyun extern int mISDN_freedchannel(struct dchannel *); 176*4882a593Smuzhiyun extern void mISDN_clear_bchannel(struct bchannel *); 177*4882a593Smuzhiyun extern void mISDN_freebchannel(struct bchannel *); 178*4882a593Smuzhiyun extern int mISDN_ctrl_bchannel(struct bchannel *, struct mISDN_ctrl_req *); 179*4882a593Smuzhiyun extern void queue_ch_frame(struct mISDNchannel *, u_int, 180*4882a593Smuzhiyun int, struct sk_buff *); 181*4882a593Smuzhiyun extern int dchannel_senddata(struct dchannel *, struct sk_buff *); 182*4882a593Smuzhiyun extern int bchannel_senddata(struct bchannel *, struct sk_buff *); 183*4882a593Smuzhiyun extern int bchannel_get_rxbuf(struct bchannel *, int); 184*4882a593Smuzhiyun extern void recv_Dchannel(struct dchannel *); 185*4882a593Smuzhiyun extern void recv_Echannel(struct dchannel *, struct dchannel *); 186*4882a593Smuzhiyun extern void recv_Bchannel(struct bchannel *, unsigned int, bool); 187*4882a593Smuzhiyun extern void recv_Dchannel_skb(struct dchannel *, struct sk_buff *); 188*4882a593Smuzhiyun extern void recv_Bchannel_skb(struct bchannel *, struct sk_buff *); 189*4882a593Smuzhiyun extern int get_next_bframe(struct bchannel *); 190*4882a593Smuzhiyun extern int get_next_dframe(struct dchannel *); 191*4882a593Smuzhiyun 192*4882a593Smuzhiyun #endif 193