1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __LIS3LV02D_H_ 3*4882a593Smuzhiyun #define __LIS3LV02D_H_ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /** 6*4882a593Smuzhiyun * struct lis3lv02d_platform_data - lis3 chip family platform data 7*4882a593Smuzhiyun * @click_flags: Click detection unit configuration 8*4882a593Smuzhiyun * @click_thresh_x: Click detection unit x axis threshold 9*4882a593Smuzhiyun * @click_thresh_y: Click detection unit y axis threshold 10*4882a593Smuzhiyun * @click_thresh_z: Click detection unit z axis threshold 11*4882a593Smuzhiyun * @click_time_limit: Click detection unit time parameter 12*4882a593Smuzhiyun * @click_latency: Click detection unit latency parameter 13*4882a593Smuzhiyun * @click_window: Click detection unit window parameter 14*4882a593Smuzhiyun * @irq_cfg: On chip irq source and type configuration (click / 15*4882a593Smuzhiyun * data available / wake up, open drain, polarity) 16*4882a593Smuzhiyun * @irq_flags1: Additional irq triggering flags for irq channel 0 17*4882a593Smuzhiyun * @irq_flags2: Additional irq triggering flags for irq channel 1 18*4882a593Smuzhiyun * @duration1: Wake up unit 1 duration parameter 19*4882a593Smuzhiyun * @duration2: Wake up unit 2 duration parameter 20*4882a593Smuzhiyun * @wakeup_flags: Wake up unit 1 flags 21*4882a593Smuzhiyun * @wakeup_thresh: Wake up unit 1 threshold value 22*4882a593Smuzhiyun * @wakeup_flags2: Wake up unit 2 flags 23*4882a593Smuzhiyun * @wakeup_thresh2: Wake up unit 2 threshold value 24*4882a593Smuzhiyun * @hipass_ctrl: High pass filter control (enable / disable, cut off 25*4882a593Smuzhiyun * frequency) 26*4882a593Smuzhiyun * @axis_x: Sensor orientation remapping for x-axis 27*4882a593Smuzhiyun * @axis_y: Sensor orientation remapping for y-axis 28*4882a593Smuzhiyun * @axis_z: Sensor orientation remapping for z-axis 29*4882a593Smuzhiyun * @driver_features: Enable bits for different features. Disabled by default 30*4882a593Smuzhiyun * @default_rate: Default sampling rate. 0 means reset default 31*4882a593Smuzhiyun * @setup_resources: Interrupt line setup call back function 32*4882a593Smuzhiyun * @release_resources: Interrupt line release call back function 33*4882a593Smuzhiyun * @st_min_limits[3]: Selftest acceptance minimum values 34*4882a593Smuzhiyun * @st_max_limits[3]: Selftest acceptance maximum values 35*4882a593Smuzhiyun * @irq2: Irq line 2 number 36*4882a593Smuzhiyun * 37*4882a593Smuzhiyun * Platform data is used to setup the sensor chip. Meaning of the different 38*4882a593Smuzhiyun * chip features can be found from the data sheet. It is publicly available 39*4882a593Smuzhiyun * at www.st.com web pages. Currently the platform data is used 40*4882a593Smuzhiyun * only for the 8 bit device. The 8 bit device has two wake up / free fall 41*4882a593Smuzhiyun * detection units and click detection unit. There are plenty of ways to 42*4882a593Smuzhiyun * configure the chip which makes is quite hard to explain deeper meaning of 43*4882a593Smuzhiyun * the fields here. Behaviour of the detection blocks varies heavily depending 44*4882a593Smuzhiyun * on the configuration. For example, interrupt detection block can use high 45*4882a593Smuzhiyun * pass filtered data which makes it react to the changes in the acceleration. 46*4882a593Smuzhiyun * Irq_flags can be used to enable interrupt detection on the both edges. 47*4882a593Smuzhiyun * With proper chip configuration this produces interrupt when some trigger 48*4882a593Smuzhiyun * starts and when it goes away. 49*4882a593Smuzhiyun */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct lis3lv02d_platform_data { 52*4882a593Smuzhiyun /* please note: the 'click' feature is only supported for 53*4882a593Smuzhiyun * LIS[32]02DL variants of the chip and will be ignored for 54*4882a593Smuzhiyun * others */ 55*4882a593Smuzhiyun #define LIS3_CLICK_SINGLE_X (1 << 0) 56*4882a593Smuzhiyun #define LIS3_CLICK_DOUBLE_X (1 << 1) 57*4882a593Smuzhiyun #define LIS3_CLICK_SINGLE_Y (1 << 2) 58*4882a593Smuzhiyun #define LIS3_CLICK_DOUBLE_Y (1 << 3) 59*4882a593Smuzhiyun #define LIS3_CLICK_SINGLE_Z (1 << 4) 60*4882a593Smuzhiyun #define LIS3_CLICK_DOUBLE_Z (1 << 5) 61*4882a593Smuzhiyun unsigned char click_flags; 62*4882a593Smuzhiyun unsigned char click_thresh_x; 63*4882a593Smuzhiyun unsigned char click_thresh_y; 64*4882a593Smuzhiyun unsigned char click_thresh_z; 65*4882a593Smuzhiyun unsigned char click_time_limit; 66*4882a593Smuzhiyun unsigned char click_latency; 67*4882a593Smuzhiyun unsigned char click_window; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define LIS3_IRQ1_DISABLE (0 << 0) 70*4882a593Smuzhiyun #define LIS3_IRQ1_FF_WU_1 (1 << 0) 71*4882a593Smuzhiyun #define LIS3_IRQ1_FF_WU_2 (2 << 0) 72*4882a593Smuzhiyun #define LIS3_IRQ1_FF_WU_12 (3 << 0) 73*4882a593Smuzhiyun #define LIS3_IRQ1_DATA_READY (4 << 0) 74*4882a593Smuzhiyun #define LIS3_IRQ1_CLICK (7 << 0) 75*4882a593Smuzhiyun #define LIS3_IRQ1_MASK (7 << 0) 76*4882a593Smuzhiyun #define LIS3_IRQ2_DISABLE (0 << 3) 77*4882a593Smuzhiyun #define LIS3_IRQ2_FF_WU_1 (1 << 3) 78*4882a593Smuzhiyun #define LIS3_IRQ2_FF_WU_2 (2 << 3) 79*4882a593Smuzhiyun #define LIS3_IRQ2_FF_WU_12 (3 << 3) 80*4882a593Smuzhiyun #define LIS3_IRQ2_DATA_READY (4 << 3) 81*4882a593Smuzhiyun #define LIS3_IRQ2_CLICK (7 << 3) 82*4882a593Smuzhiyun #define LIS3_IRQ2_MASK (7 << 3) 83*4882a593Smuzhiyun #define LIS3_IRQ_OPEN_DRAIN (1 << 6) 84*4882a593Smuzhiyun #define LIS3_IRQ_ACTIVE_LOW (1 << 7) 85*4882a593Smuzhiyun unsigned char irq_cfg; 86*4882a593Smuzhiyun unsigned char irq_flags1; /* Additional irq edge / level flags */ 87*4882a593Smuzhiyun unsigned char irq_flags2; /* Additional irq edge / level flags */ 88*4882a593Smuzhiyun unsigned char duration1; 89*4882a593Smuzhiyun unsigned char duration2; 90*4882a593Smuzhiyun #define LIS3_WAKEUP_X_LO (1 << 0) 91*4882a593Smuzhiyun #define LIS3_WAKEUP_X_HI (1 << 1) 92*4882a593Smuzhiyun #define LIS3_WAKEUP_Y_LO (1 << 2) 93*4882a593Smuzhiyun #define LIS3_WAKEUP_Y_HI (1 << 3) 94*4882a593Smuzhiyun #define LIS3_WAKEUP_Z_LO (1 << 4) 95*4882a593Smuzhiyun #define LIS3_WAKEUP_Z_HI (1 << 5) 96*4882a593Smuzhiyun unsigned char wakeup_flags; 97*4882a593Smuzhiyun unsigned char wakeup_thresh; 98*4882a593Smuzhiyun unsigned char wakeup_flags2; 99*4882a593Smuzhiyun unsigned char wakeup_thresh2; 100*4882a593Smuzhiyun #define LIS3_HIPASS_CUTFF_8HZ 0 101*4882a593Smuzhiyun #define LIS3_HIPASS_CUTFF_4HZ 1 102*4882a593Smuzhiyun #define LIS3_HIPASS_CUTFF_2HZ 2 103*4882a593Smuzhiyun #define LIS3_HIPASS_CUTFF_1HZ 3 104*4882a593Smuzhiyun #define LIS3_HIPASS1_DISABLE (1 << 2) 105*4882a593Smuzhiyun #define LIS3_HIPASS2_DISABLE (1 << 3) 106*4882a593Smuzhiyun unsigned char hipass_ctrl; 107*4882a593Smuzhiyun #define LIS3_NO_MAP 0 108*4882a593Smuzhiyun #define LIS3_DEV_X 1 109*4882a593Smuzhiyun #define LIS3_DEV_Y 2 110*4882a593Smuzhiyun #define LIS3_DEV_Z 3 111*4882a593Smuzhiyun #define LIS3_INV_DEV_X -1 112*4882a593Smuzhiyun #define LIS3_INV_DEV_Y -2 113*4882a593Smuzhiyun #define LIS3_INV_DEV_Z -3 114*4882a593Smuzhiyun s8 axis_x; 115*4882a593Smuzhiyun s8 axis_y; 116*4882a593Smuzhiyun s8 axis_z; 117*4882a593Smuzhiyun #define LIS3_USE_BLOCK_READ 0x02 118*4882a593Smuzhiyun u16 driver_features; 119*4882a593Smuzhiyun int default_rate; 120*4882a593Smuzhiyun int (*setup_resources)(void); 121*4882a593Smuzhiyun int (*release_resources)(void); 122*4882a593Smuzhiyun /* Limits for selftest are specified in chip data sheet */ 123*4882a593Smuzhiyun s16 st_min_limits[3]; /* min pass limit x, y, z */ 124*4882a593Smuzhiyun s16 st_max_limits[3]; /* max pass limit x, y, z */ 125*4882a593Smuzhiyun int irq2; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun #endif /* __LIS3LV02D_H_ */ 129