1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * libnvdimm - Non-volatile-memory Devices Subsystem
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright(c) 2013-2015 Intel Corporation. All rights reserved.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun #ifndef __LIBNVDIMM_H__
8*4882a593Smuzhiyun #define __LIBNVDIMM_H__
9*4882a593Smuzhiyun #include <linux/kernel.h>
10*4882a593Smuzhiyun #include <linux/sizes.h>
11*4882a593Smuzhiyun #include <linux/types.h>
12*4882a593Smuzhiyun #include <linux/uuid.h>
13*4882a593Smuzhiyun #include <linux/spinlock.h>
14*4882a593Smuzhiyun #include <linux/bio.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct badrange_entry {
17*4882a593Smuzhiyun u64 start;
18*4882a593Smuzhiyun u64 length;
19*4882a593Smuzhiyun struct list_head list;
20*4882a593Smuzhiyun };
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun struct badrange {
23*4882a593Smuzhiyun struct list_head list;
24*4882a593Smuzhiyun spinlock_t lock;
25*4882a593Smuzhiyun };
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun enum {
28*4882a593Smuzhiyun /* when a dimm supports both PMEM and BLK access a label is required */
29*4882a593Smuzhiyun NDD_ALIASING = 0,
30*4882a593Smuzhiyun /* unarmed memory devices may not persist writes */
31*4882a593Smuzhiyun NDD_UNARMED = 1,
32*4882a593Smuzhiyun /* locked memory devices should not be accessed */
33*4882a593Smuzhiyun NDD_LOCKED = 2,
34*4882a593Smuzhiyun /* memory under security wipes should not be accessed */
35*4882a593Smuzhiyun NDD_SECURITY_OVERWRITE = 3,
36*4882a593Smuzhiyun /* tracking whether or not there is a pending device reference */
37*4882a593Smuzhiyun NDD_WORK_PENDING = 4,
38*4882a593Smuzhiyun /* ignore / filter NSLABEL_FLAG_LOCAL for this DIMM, i.e. no aliasing */
39*4882a593Smuzhiyun NDD_NOBLK = 5,
40*4882a593Smuzhiyun /* dimm supports namespace labels */
41*4882a593Smuzhiyun NDD_LABELING = 6,
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* need to set a limit somewhere, but yes, this is likely overkill */
44*4882a593Smuzhiyun ND_IOCTL_MAX_BUFLEN = SZ_4M,
45*4882a593Smuzhiyun ND_CMD_MAX_ELEM = 5,
46*4882a593Smuzhiyun ND_CMD_MAX_ENVELOPE = 256,
47*4882a593Smuzhiyun ND_MAX_MAPPINGS = 32,
48*4882a593Smuzhiyun
49*4882a593Smuzhiyun /* region flag indicating to direct-map persistent memory by default */
50*4882a593Smuzhiyun ND_REGION_PAGEMAP = 0,
51*4882a593Smuzhiyun /*
52*4882a593Smuzhiyun * Platform ensures entire CPU store data path is flushed to pmem on
53*4882a593Smuzhiyun * system power loss.
54*4882a593Smuzhiyun */
55*4882a593Smuzhiyun ND_REGION_PERSIST_CACHE = 1,
56*4882a593Smuzhiyun /*
57*4882a593Smuzhiyun * Platform provides mechanisms to automatically flush outstanding
58*4882a593Smuzhiyun * write data from memory controler to pmem on system power loss.
59*4882a593Smuzhiyun * (ADR)
60*4882a593Smuzhiyun */
61*4882a593Smuzhiyun ND_REGION_PERSIST_MEMCTRL = 2,
62*4882a593Smuzhiyun
63*4882a593Smuzhiyun /* Platform provides asynchronous flush mechanism */
64*4882a593Smuzhiyun ND_REGION_ASYNC = 3,
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun /* mark newly adjusted resources as requiring a label update */
67*4882a593Smuzhiyun DPA_RESOURCE_ADJUSTED = 1 << 0,
68*4882a593Smuzhiyun };
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct nvdimm;
71*4882a593Smuzhiyun struct nvdimm_bus_descriptor;
72*4882a593Smuzhiyun typedef int (*ndctl_fn)(struct nvdimm_bus_descriptor *nd_desc,
73*4882a593Smuzhiyun struct nvdimm *nvdimm, unsigned int cmd, void *buf,
74*4882a593Smuzhiyun unsigned int buf_len, int *cmd_rc);
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun struct device_node;
77*4882a593Smuzhiyun struct nvdimm_bus_descriptor {
78*4882a593Smuzhiyun const struct attribute_group **attr_groups;
79*4882a593Smuzhiyun unsigned long cmd_mask;
80*4882a593Smuzhiyun unsigned long dimm_family_mask;
81*4882a593Smuzhiyun unsigned long bus_family_mask;
82*4882a593Smuzhiyun struct module *module;
83*4882a593Smuzhiyun char *provider_name;
84*4882a593Smuzhiyun struct device_node *of_node;
85*4882a593Smuzhiyun ndctl_fn ndctl;
86*4882a593Smuzhiyun int (*flush_probe)(struct nvdimm_bus_descriptor *nd_desc);
87*4882a593Smuzhiyun int (*clear_to_send)(struct nvdimm_bus_descriptor *nd_desc,
88*4882a593Smuzhiyun struct nvdimm *nvdimm, unsigned int cmd, void *data);
89*4882a593Smuzhiyun const struct nvdimm_bus_fw_ops *fw_ops;
90*4882a593Smuzhiyun };
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun struct nd_cmd_desc {
93*4882a593Smuzhiyun int in_num;
94*4882a593Smuzhiyun int out_num;
95*4882a593Smuzhiyun u32 in_sizes[ND_CMD_MAX_ELEM];
96*4882a593Smuzhiyun int out_sizes[ND_CMD_MAX_ELEM];
97*4882a593Smuzhiyun };
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun struct nd_interleave_set {
100*4882a593Smuzhiyun /* v1.1 definition of the interleave-set-cookie algorithm */
101*4882a593Smuzhiyun u64 cookie1;
102*4882a593Smuzhiyun /* v1.2 definition of the interleave-set-cookie algorithm */
103*4882a593Smuzhiyun u64 cookie2;
104*4882a593Smuzhiyun /* compatibility with initial buggy Linux implementation */
105*4882a593Smuzhiyun u64 altcookie;
106*4882a593Smuzhiyun
107*4882a593Smuzhiyun guid_t type_guid;
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun struct nd_mapping_desc {
111*4882a593Smuzhiyun struct nvdimm *nvdimm;
112*4882a593Smuzhiyun u64 start;
113*4882a593Smuzhiyun u64 size;
114*4882a593Smuzhiyun int position;
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun struct nd_region;
118*4882a593Smuzhiyun struct nd_region_desc {
119*4882a593Smuzhiyun struct resource *res;
120*4882a593Smuzhiyun struct nd_mapping_desc *mapping;
121*4882a593Smuzhiyun u16 num_mappings;
122*4882a593Smuzhiyun const struct attribute_group **attr_groups;
123*4882a593Smuzhiyun struct nd_interleave_set *nd_set;
124*4882a593Smuzhiyun void *provider_data;
125*4882a593Smuzhiyun int num_lanes;
126*4882a593Smuzhiyun int numa_node;
127*4882a593Smuzhiyun int target_node;
128*4882a593Smuzhiyun unsigned long flags;
129*4882a593Smuzhiyun struct device_node *of_node;
130*4882a593Smuzhiyun int (*flush)(struct nd_region *nd_region, struct bio *bio);
131*4882a593Smuzhiyun };
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun struct device;
134*4882a593Smuzhiyun void *devm_nvdimm_memremap(struct device *dev, resource_size_t offset,
135*4882a593Smuzhiyun size_t size, unsigned long flags);
devm_nvdimm_ioremap(struct device * dev,resource_size_t offset,size_t size)136*4882a593Smuzhiyun static inline void __iomem *devm_nvdimm_ioremap(struct device *dev,
137*4882a593Smuzhiyun resource_size_t offset, size_t size)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun return (void __iomem *) devm_nvdimm_memremap(dev, offset, size, 0);
140*4882a593Smuzhiyun }
141*4882a593Smuzhiyun
142*4882a593Smuzhiyun struct nvdimm_bus;
143*4882a593Smuzhiyun struct module;
144*4882a593Smuzhiyun struct device;
145*4882a593Smuzhiyun struct nd_blk_region;
146*4882a593Smuzhiyun struct nd_blk_region_desc {
147*4882a593Smuzhiyun int (*enable)(struct nvdimm_bus *nvdimm_bus, struct device *dev);
148*4882a593Smuzhiyun int (*do_io)(struct nd_blk_region *ndbr, resource_size_t dpa,
149*4882a593Smuzhiyun void *iobuf, u64 len, int rw);
150*4882a593Smuzhiyun struct nd_region_desc ndr_desc;
151*4882a593Smuzhiyun };
152*4882a593Smuzhiyun
to_blk_region_desc(struct nd_region_desc * ndr_desc)153*4882a593Smuzhiyun static inline struct nd_blk_region_desc *to_blk_region_desc(
154*4882a593Smuzhiyun struct nd_region_desc *ndr_desc)
155*4882a593Smuzhiyun {
156*4882a593Smuzhiyun return container_of(ndr_desc, struct nd_blk_region_desc, ndr_desc);
157*4882a593Smuzhiyun
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun /*
161*4882a593Smuzhiyun * Note that separate bits for locked + unlocked are defined so that
162*4882a593Smuzhiyun * 'flags == 0' corresponds to an error / not-supported state.
163*4882a593Smuzhiyun */
164*4882a593Smuzhiyun enum nvdimm_security_bits {
165*4882a593Smuzhiyun NVDIMM_SECURITY_DISABLED,
166*4882a593Smuzhiyun NVDIMM_SECURITY_UNLOCKED,
167*4882a593Smuzhiyun NVDIMM_SECURITY_LOCKED,
168*4882a593Smuzhiyun NVDIMM_SECURITY_FROZEN,
169*4882a593Smuzhiyun NVDIMM_SECURITY_OVERWRITE,
170*4882a593Smuzhiyun };
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun #define NVDIMM_PASSPHRASE_LEN 32
173*4882a593Smuzhiyun #define NVDIMM_KEY_DESC_LEN 22
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun struct nvdimm_key_data {
176*4882a593Smuzhiyun u8 data[NVDIMM_PASSPHRASE_LEN];
177*4882a593Smuzhiyun };
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun enum nvdimm_passphrase_type {
180*4882a593Smuzhiyun NVDIMM_USER,
181*4882a593Smuzhiyun NVDIMM_MASTER,
182*4882a593Smuzhiyun };
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun struct nvdimm_security_ops {
185*4882a593Smuzhiyun unsigned long (*get_flags)(struct nvdimm *nvdimm,
186*4882a593Smuzhiyun enum nvdimm_passphrase_type pass_type);
187*4882a593Smuzhiyun int (*freeze)(struct nvdimm *nvdimm);
188*4882a593Smuzhiyun int (*change_key)(struct nvdimm *nvdimm,
189*4882a593Smuzhiyun const struct nvdimm_key_data *old_data,
190*4882a593Smuzhiyun const struct nvdimm_key_data *new_data,
191*4882a593Smuzhiyun enum nvdimm_passphrase_type pass_type);
192*4882a593Smuzhiyun int (*unlock)(struct nvdimm *nvdimm,
193*4882a593Smuzhiyun const struct nvdimm_key_data *key_data);
194*4882a593Smuzhiyun int (*disable)(struct nvdimm *nvdimm,
195*4882a593Smuzhiyun const struct nvdimm_key_data *key_data);
196*4882a593Smuzhiyun int (*erase)(struct nvdimm *nvdimm,
197*4882a593Smuzhiyun const struct nvdimm_key_data *key_data,
198*4882a593Smuzhiyun enum nvdimm_passphrase_type pass_type);
199*4882a593Smuzhiyun int (*overwrite)(struct nvdimm *nvdimm,
200*4882a593Smuzhiyun const struct nvdimm_key_data *key_data);
201*4882a593Smuzhiyun int (*query_overwrite)(struct nvdimm *nvdimm);
202*4882a593Smuzhiyun };
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun enum nvdimm_fwa_state {
205*4882a593Smuzhiyun NVDIMM_FWA_INVALID,
206*4882a593Smuzhiyun NVDIMM_FWA_IDLE,
207*4882a593Smuzhiyun NVDIMM_FWA_ARMED,
208*4882a593Smuzhiyun NVDIMM_FWA_BUSY,
209*4882a593Smuzhiyun NVDIMM_FWA_ARM_OVERFLOW,
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun enum nvdimm_fwa_trigger {
213*4882a593Smuzhiyun NVDIMM_FWA_ARM,
214*4882a593Smuzhiyun NVDIMM_FWA_DISARM,
215*4882a593Smuzhiyun };
216*4882a593Smuzhiyun
217*4882a593Smuzhiyun enum nvdimm_fwa_capability {
218*4882a593Smuzhiyun NVDIMM_FWA_CAP_INVALID,
219*4882a593Smuzhiyun NVDIMM_FWA_CAP_NONE,
220*4882a593Smuzhiyun NVDIMM_FWA_CAP_QUIESCE,
221*4882a593Smuzhiyun NVDIMM_FWA_CAP_LIVE,
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun
224*4882a593Smuzhiyun enum nvdimm_fwa_result {
225*4882a593Smuzhiyun NVDIMM_FWA_RESULT_INVALID,
226*4882a593Smuzhiyun NVDIMM_FWA_RESULT_NONE,
227*4882a593Smuzhiyun NVDIMM_FWA_RESULT_SUCCESS,
228*4882a593Smuzhiyun NVDIMM_FWA_RESULT_NOTSTAGED,
229*4882a593Smuzhiyun NVDIMM_FWA_RESULT_NEEDRESET,
230*4882a593Smuzhiyun NVDIMM_FWA_RESULT_FAIL,
231*4882a593Smuzhiyun };
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun struct nvdimm_bus_fw_ops {
234*4882a593Smuzhiyun enum nvdimm_fwa_state (*activate_state)
235*4882a593Smuzhiyun (struct nvdimm_bus_descriptor *nd_desc);
236*4882a593Smuzhiyun enum nvdimm_fwa_capability (*capability)
237*4882a593Smuzhiyun (struct nvdimm_bus_descriptor *nd_desc);
238*4882a593Smuzhiyun int (*activate)(struct nvdimm_bus_descriptor *nd_desc);
239*4882a593Smuzhiyun };
240*4882a593Smuzhiyun
241*4882a593Smuzhiyun struct nvdimm_fw_ops {
242*4882a593Smuzhiyun enum nvdimm_fwa_state (*activate_state)(struct nvdimm *nvdimm);
243*4882a593Smuzhiyun enum nvdimm_fwa_result (*activate_result)(struct nvdimm *nvdimm);
244*4882a593Smuzhiyun int (*arm)(struct nvdimm *nvdimm, enum nvdimm_fwa_trigger arg);
245*4882a593Smuzhiyun };
246*4882a593Smuzhiyun
247*4882a593Smuzhiyun void badrange_init(struct badrange *badrange);
248*4882a593Smuzhiyun int badrange_add(struct badrange *badrange, u64 addr, u64 length);
249*4882a593Smuzhiyun void badrange_forget(struct badrange *badrange, phys_addr_t start,
250*4882a593Smuzhiyun unsigned int len);
251*4882a593Smuzhiyun int nvdimm_bus_add_badrange(struct nvdimm_bus *nvdimm_bus, u64 addr,
252*4882a593Smuzhiyun u64 length);
253*4882a593Smuzhiyun struct nvdimm_bus *nvdimm_bus_register(struct device *parent,
254*4882a593Smuzhiyun struct nvdimm_bus_descriptor *nfit_desc);
255*4882a593Smuzhiyun void nvdimm_bus_unregister(struct nvdimm_bus *nvdimm_bus);
256*4882a593Smuzhiyun struct nvdimm_bus *to_nvdimm_bus(struct device *dev);
257*4882a593Smuzhiyun struct nvdimm_bus *nvdimm_to_bus(struct nvdimm *nvdimm);
258*4882a593Smuzhiyun struct nvdimm *to_nvdimm(struct device *dev);
259*4882a593Smuzhiyun struct nd_region *to_nd_region(struct device *dev);
260*4882a593Smuzhiyun struct device *nd_region_dev(struct nd_region *nd_region);
261*4882a593Smuzhiyun struct nd_blk_region *to_nd_blk_region(struct device *dev);
262*4882a593Smuzhiyun struct nvdimm_bus_descriptor *to_nd_desc(struct nvdimm_bus *nvdimm_bus);
263*4882a593Smuzhiyun struct device *to_nvdimm_bus_dev(struct nvdimm_bus *nvdimm_bus);
264*4882a593Smuzhiyun const char *nvdimm_name(struct nvdimm *nvdimm);
265*4882a593Smuzhiyun struct kobject *nvdimm_kobj(struct nvdimm *nvdimm);
266*4882a593Smuzhiyun unsigned long nvdimm_cmd_mask(struct nvdimm *nvdimm);
267*4882a593Smuzhiyun void *nvdimm_provider_data(struct nvdimm *nvdimm);
268*4882a593Smuzhiyun struct nvdimm *__nvdimm_create(struct nvdimm_bus *nvdimm_bus,
269*4882a593Smuzhiyun void *provider_data, const struct attribute_group **groups,
270*4882a593Smuzhiyun unsigned long flags, unsigned long cmd_mask, int num_flush,
271*4882a593Smuzhiyun struct resource *flush_wpq, const char *dimm_id,
272*4882a593Smuzhiyun const struct nvdimm_security_ops *sec_ops,
273*4882a593Smuzhiyun const struct nvdimm_fw_ops *fw_ops);
nvdimm_create(struct nvdimm_bus * nvdimm_bus,void * provider_data,const struct attribute_group ** groups,unsigned long flags,unsigned long cmd_mask,int num_flush,struct resource * flush_wpq)274*4882a593Smuzhiyun static inline struct nvdimm *nvdimm_create(struct nvdimm_bus *nvdimm_bus,
275*4882a593Smuzhiyun void *provider_data, const struct attribute_group **groups,
276*4882a593Smuzhiyun unsigned long flags, unsigned long cmd_mask, int num_flush,
277*4882a593Smuzhiyun struct resource *flush_wpq)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun return __nvdimm_create(nvdimm_bus, provider_data, groups, flags,
280*4882a593Smuzhiyun cmd_mask, num_flush, flush_wpq, NULL, NULL, NULL);
281*4882a593Smuzhiyun }
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun const struct nd_cmd_desc *nd_cmd_dimm_desc(int cmd);
284*4882a593Smuzhiyun const struct nd_cmd_desc *nd_cmd_bus_desc(int cmd);
285*4882a593Smuzhiyun u32 nd_cmd_in_size(struct nvdimm *nvdimm, int cmd,
286*4882a593Smuzhiyun const struct nd_cmd_desc *desc, int idx, void *buf);
287*4882a593Smuzhiyun u32 nd_cmd_out_size(struct nvdimm *nvdimm, int cmd,
288*4882a593Smuzhiyun const struct nd_cmd_desc *desc, int idx, const u32 *in_field,
289*4882a593Smuzhiyun const u32 *out_field, unsigned long remainder);
290*4882a593Smuzhiyun int nvdimm_bus_check_dimm_count(struct nvdimm_bus *nvdimm_bus, int dimm_count);
291*4882a593Smuzhiyun struct nd_region *nvdimm_pmem_region_create(struct nvdimm_bus *nvdimm_bus,
292*4882a593Smuzhiyun struct nd_region_desc *ndr_desc);
293*4882a593Smuzhiyun struct nd_region *nvdimm_blk_region_create(struct nvdimm_bus *nvdimm_bus,
294*4882a593Smuzhiyun struct nd_region_desc *ndr_desc);
295*4882a593Smuzhiyun struct nd_region *nvdimm_volatile_region_create(struct nvdimm_bus *nvdimm_bus,
296*4882a593Smuzhiyun struct nd_region_desc *ndr_desc);
297*4882a593Smuzhiyun void *nd_region_provider_data(struct nd_region *nd_region);
298*4882a593Smuzhiyun void *nd_blk_region_provider_data(struct nd_blk_region *ndbr);
299*4882a593Smuzhiyun void nd_blk_region_set_provider_data(struct nd_blk_region *ndbr, void *data);
300*4882a593Smuzhiyun struct nvdimm *nd_blk_region_to_dimm(struct nd_blk_region *ndbr);
301*4882a593Smuzhiyun unsigned long nd_blk_memremap_flags(struct nd_blk_region *ndbr);
302*4882a593Smuzhiyun unsigned int nd_region_acquire_lane(struct nd_region *nd_region);
303*4882a593Smuzhiyun void nd_region_release_lane(struct nd_region *nd_region, unsigned int lane);
304*4882a593Smuzhiyun u64 nd_fletcher64(void *addr, size_t len, bool le);
305*4882a593Smuzhiyun int nvdimm_flush(struct nd_region *nd_region, struct bio *bio);
306*4882a593Smuzhiyun int generic_nvdimm_flush(struct nd_region *nd_region);
307*4882a593Smuzhiyun int nvdimm_has_flush(struct nd_region *nd_region);
308*4882a593Smuzhiyun int nvdimm_has_cache(struct nd_region *nd_region);
309*4882a593Smuzhiyun int nvdimm_in_overwrite(struct nvdimm *nvdimm);
310*4882a593Smuzhiyun bool is_nvdimm_sync(struct nd_region *nd_region);
311*4882a593Smuzhiyun
nvdimm_ctl(struct nvdimm * nvdimm,unsigned int cmd,void * buf,unsigned int buf_len,int * cmd_rc)312*4882a593Smuzhiyun static inline int nvdimm_ctl(struct nvdimm *nvdimm, unsigned int cmd, void *buf,
313*4882a593Smuzhiyun unsigned int buf_len, int *cmd_rc)
314*4882a593Smuzhiyun {
315*4882a593Smuzhiyun struct nvdimm_bus *nvdimm_bus = nvdimm_to_bus(nvdimm);
316*4882a593Smuzhiyun struct nvdimm_bus_descriptor *nd_desc = to_nd_desc(nvdimm_bus);
317*4882a593Smuzhiyun
318*4882a593Smuzhiyun return nd_desc->ndctl(nd_desc, nvdimm, cmd, buf, buf_len, cmd_rc);
319*4882a593Smuzhiyun }
320*4882a593Smuzhiyun
321*4882a593Smuzhiyun #ifdef CONFIG_ARCH_HAS_PMEM_API
322*4882a593Smuzhiyun #define ARCH_MEMREMAP_PMEM MEMREMAP_WB
323*4882a593Smuzhiyun void arch_wb_cache_pmem(void *addr, size_t size);
324*4882a593Smuzhiyun void arch_invalidate_pmem(void *addr, size_t size);
325*4882a593Smuzhiyun #else
326*4882a593Smuzhiyun #define ARCH_MEMREMAP_PMEM MEMREMAP_WT
arch_wb_cache_pmem(void * addr,size_t size)327*4882a593Smuzhiyun static inline void arch_wb_cache_pmem(void *addr, size_t size)
328*4882a593Smuzhiyun {
329*4882a593Smuzhiyun }
arch_invalidate_pmem(void * addr,size_t size)330*4882a593Smuzhiyun static inline void arch_invalidate_pmem(void *addr, size_t size)
331*4882a593Smuzhiyun {
332*4882a593Smuzhiyun }
333*4882a593Smuzhiyun #endif
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun #endif /* __LIBNVDIMM_H__ */
336