1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * LED driver for TI lp3952 controller 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016, DAQRI, LLC. 6*4882a593Smuzhiyun * Author: Tony Makkiel <tony.makkiel@daqri.com> 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef LEDS_LP3952_H_ 10*4882a593Smuzhiyun #define LEDS_LP3952_H_ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define LP3952_NAME "lp3952" 13*4882a593Smuzhiyun #define LP3952_CMD_REG_COUNT 8 14*4882a593Smuzhiyun #define LP3952_BRIGHT_MAX 4 15*4882a593Smuzhiyun #define LP3952_LABEL_MAX_LEN 15 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #define LP3952_REG_LED_CTRL 0x00 18*4882a593Smuzhiyun #define LP3952_REG_R1_BLNK_TIME_CTRL 0x01 19*4882a593Smuzhiyun #define LP3952_REG_R1_BLNK_CYCLE_CTRL 0x02 20*4882a593Smuzhiyun #define LP3952_REG_G1_BLNK_TIME_CTRL 0x03 21*4882a593Smuzhiyun #define LP3952_REG_G1_BLNK_CYCLE_CTRL 0x04 22*4882a593Smuzhiyun #define LP3952_REG_B1_BLNK_TIME_CTRL 0x05 23*4882a593Smuzhiyun #define LP3952_REG_B1_BLNK_CYCLE_CTRL 0x06 24*4882a593Smuzhiyun #define LP3952_REG_ENABLES 0x0B 25*4882a593Smuzhiyun #define LP3952_REG_PAT_GEN_CTRL 0x11 26*4882a593Smuzhiyun #define LP3952_REG_RGB1_MAX_I_CTRL 0x12 27*4882a593Smuzhiyun #define LP3952_REG_RGB2_MAX_I_CTRL 0x13 28*4882a593Smuzhiyun #define LP3952_REG_CMD_0 0x50 29*4882a593Smuzhiyun #define LP3952_REG_RESET 0x60 30*4882a593Smuzhiyun #define REG_MAX LP3952_REG_RESET 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define LP3952_PATRN_LOOP BIT(1) 33*4882a593Smuzhiyun #define LP3952_PATRN_GEN_EN BIT(2) 34*4882a593Smuzhiyun #define LP3952_INT_B00ST_LDR BIT(2) 35*4882a593Smuzhiyun #define LP3952_ACTIVE_MODE BIT(6) 36*4882a593Smuzhiyun #define LP3952_LED_MASK_ALL 0x3f 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun /* Transition Time in ms */ 39*4882a593Smuzhiyun enum lp3952_tt { 40*4882a593Smuzhiyun TT0, 41*4882a593Smuzhiyun TT55, 42*4882a593Smuzhiyun TT110, 43*4882a593Smuzhiyun TT221, 44*4882a593Smuzhiyun TT422, 45*4882a593Smuzhiyun TT885, 46*4882a593Smuzhiyun TT1770, 47*4882a593Smuzhiyun TT3539 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* Command Execution Time in ms */ 51*4882a593Smuzhiyun enum lp3952_cet { 52*4882a593Smuzhiyun CET197, 53*4882a593Smuzhiyun CET393, 54*4882a593Smuzhiyun CET590, 55*4882a593Smuzhiyun CET786, 56*4882a593Smuzhiyun CET1180, 57*4882a593Smuzhiyun CET1376, 58*4882a593Smuzhiyun CET1573, 59*4882a593Smuzhiyun CET1769, 60*4882a593Smuzhiyun CET1966, 61*4882a593Smuzhiyun CET2163, 62*4882a593Smuzhiyun CET2359, 63*4882a593Smuzhiyun CET2556, 64*4882a593Smuzhiyun CET2763, 65*4882a593Smuzhiyun CET2949, 66*4882a593Smuzhiyun CET3146 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun /* Max Current in % */ 70*4882a593Smuzhiyun enum lp3952_colour_I_log_0 { 71*4882a593Smuzhiyun I0, 72*4882a593Smuzhiyun I7, 73*4882a593Smuzhiyun I14, 74*4882a593Smuzhiyun I21, 75*4882a593Smuzhiyun I32, 76*4882a593Smuzhiyun I46, 77*4882a593Smuzhiyun I71, 78*4882a593Smuzhiyun I100 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun enum lp3952_leds { 82*4882a593Smuzhiyun LP3952_BLUE_2, 83*4882a593Smuzhiyun LP3952_GREEN_2, 84*4882a593Smuzhiyun LP3952_RED_2, 85*4882a593Smuzhiyun LP3952_BLUE_1, 86*4882a593Smuzhiyun LP3952_GREEN_1, 87*4882a593Smuzhiyun LP3952_RED_1, 88*4882a593Smuzhiyun LP3952_LED_ALL 89*4882a593Smuzhiyun }; 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun struct lp3952_ctrl_hdl { 92*4882a593Smuzhiyun struct led_classdev cdev; 93*4882a593Smuzhiyun char name[LP3952_LABEL_MAX_LEN]; 94*4882a593Smuzhiyun enum lp3952_leds channel; 95*4882a593Smuzhiyun void *priv; 96*4882a593Smuzhiyun }; 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun struct ptrn_gen_cmd { 99*4882a593Smuzhiyun union { 100*4882a593Smuzhiyun struct { 101*4882a593Smuzhiyun u16 tt:3; 102*4882a593Smuzhiyun u16 b:3; 103*4882a593Smuzhiyun u16 cet:4; 104*4882a593Smuzhiyun u16 g:3; 105*4882a593Smuzhiyun u16 r:3; 106*4882a593Smuzhiyun }; 107*4882a593Smuzhiyun struct { 108*4882a593Smuzhiyun u8 lsb; 109*4882a593Smuzhiyun u8 msb; 110*4882a593Smuzhiyun } bytes; 111*4882a593Smuzhiyun }; 112*4882a593Smuzhiyun } __packed; 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun struct lp3952_led_array { 115*4882a593Smuzhiyun struct regmap *regmap; 116*4882a593Smuzhiyun struct i2c_client *client; 117*4882a593Smuzhiyun struct gpio_desc *enable_gpio; 118*4882a593Smuzhiyun struct lp3952_ctrl_hdl leds[LP3952_LED_ALL]; 119*4882a593Smuzhiyun }; 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #endif /* LEDS_LP3952_H_ */ 122