1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Root interrupt controller for the BCM2836 (Raspberry Pi 2). 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2015 Broadcom 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #define LOCAL_CONTROL 0x000 9*4882a593Smuzhiyun #define LOCAL_PRESCALER 0x008 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun /* 12*4882a593Smuzhiyun * The low 2 bits identify the CPU that the GPU IRQ goes to, and the 13*4882a593Smuzhiyun * next 2 bits identify the CPU that the GPU FIQ goes to. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun #define LOCAL_GPU_ROUTING 0x00c 16*4882a593Smuzhiyun /* When setting bits 0-3, enables PMU interrupts on that CPU. */ 17*4882a593Smuzhiyun #define LOCAL_PM_ROUTING_SET 0x010 18*4882a593Smuzhiyun /* When setting bits 0-3, disables PMU interrupts on that CPU. */ 19*4882a593Smuzhiyun #define LOCAL_PM_ROUTING_CLR 0x014 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * The low 4 bits of this are the CPU's timer IRQ enables, and the 22*4882a593Smuzhiyun * next 4 bits are the CPU's timer FIQ enables (which override the IRQ 23*4882a593Smuzhiyun * bits). 24*4882a593Smuzhiyun */ 25*4882a593Smuzhiyun #define LOCAL_TIMER_INT_CONTROL0 0x040 26*4882a593Smuzhiyun /* 27*4882a593Smuzhiyun * The low 4 bits of this are the CPU's per-mailbox IRQ enables, and 28*4882a593Smuzhiyun * the next 4 bits are the CPU's per-mailbox FIQ enables (which 29*4882a593Smuzhiyun * override the IRQ bits). 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun #define LOCAL_MAILBOX_INT_CONTROL0 0x050 32*4882a593Smuzhiyun /* 33*4882a593Smuzhiyun * The CPU's interrupt status register. Bits are defined by the 34*4882a593Smuzhiyun * LOCAL_IRQ_* bits below. 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun #define LOCAL_IRQ_PENDING0 0x060 37*4882a593Smuzhiyun /* Same status bits as above, but for FIQ. */ 38*4882a593Smuzhiyun #define LOCAL_FIQ_PENDING0 0x070 39*4882a593Smuzhiyun /* 40*4882a593Smuzhiyun * Mailbox write-to-set bits. There are 16 mailboxes, 4 per CPU, and 41*4882a593Smuzhiyun * these bits are organized by mailbox number and then CPU number. We 42*4882a593Smuzhiyun * use mailbox 0 for IPIs. The mailbox's interrupt is raised while 43*4882a593Smuzhiyun * any bit is set. 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun #define LOCAL_MAILBOX0_SET0 0x080 46*4882a593Smuzhiyun #define LOCAL_MAILBOX3_SET0 0x08c 47*4882a593Smuzhiyun /* Mailbox write-to-clear bits. */ 48*4882a593Smuzhiyun #define LOCAL_MAILBOX0_CLR0 0x0c0 49*4882a593Smuzhiyun #define LOCAL_MAILBOX3_CLR0 0x0cc 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #define LOCAL_IRQ_CNTPSIRQ 0 52*4882a593Smuzhiyun #define LOCAL_IRQ_CNTPNSIRQ 1 53*4882a593Smuzhiyun #define LOCAL_IRQ_CNTHPIRQ 2 54*4882a593Smuzhiyun #define LOCAL_IRQ_CNTVIRQ 3 55*4882a593Smuzhiyun #define LOCAL_IRQ_MAILBOX0 4 56*4882a593Smuzhiyun #define LOCAL_IRQ_MAILBOX1 5 57*4882a593Smuzhiyun #define LOCAL_IRQ_MAILBOX2 6 58*4882a593Smuzhiyun #define LOCAL_IRQ_MAILBOX3 7 59*4882a593Smuzhiyun #define LOCAL_IRQ_GPU_FAST 8 60*4882a593Smuzhiyun #define LOCAL_IRQ_PMU_FAST 9 61*4882a593Smuzhiyun #define LAST_IRQ LOCAL_IRQ_PMU_FAST 62