1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Chained IRQ handlers support. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2011 ARM Ltd. 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __IRQCHIP_CHAINED_IRQ_H 8*4882a593Smuzhiyun #define __IRQCHIP_CHAINED_IRQ_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/irq.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Entry/exit functions for chained handlers where the primary IRQ chip 14*4882a593Smuzhiyun * may implement either fasteoi or level-trigger flow control. 15*4882a593Smuzhiyun */ chained_irq_enter(struct irq_chip * chip,struct irq_desc * desc)16*4882a593Smuzhiyunstatic inline void chained_irq_enter(struct irq_chip *chip, 17*4882a593Smuzhiyun struct irq_desc *desc) 18*4882a593Smuzhiyun { 19*4882a593Smuzhiyun /* FastEOI controllers require no action on entry. */ 20*4882a593Smuzhiyun if (chip->irq_eoi) 21*4882a593Smuzhiyun return; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun if (chip->irq_mask_ack) { 24*4882a593Smuzhiyun chip->irq_mask_ack(&desc->irq_data); 25*4882a593Smuzhiyun } else { 26*4882a593Smuzhiyun chip->irq_mask(&desc->irq_data); 27*4882a593Smuzhiyun if (chip->irq_ack) 28*4882a593Smuzhiyun chip->irq_ack(&desc->irq_data); 29*4882a593Smuzhiyun } 30*4882a593Smuzhiyun } 31*4882a593Smuzhiyun chained_irq_exit(struct irq_chip * chip,struct irq_desc * desc)32*4882a593Smuzhiyunstatic inline void chained_irq_exit(struct irq_chip *chip, 33*4882a593Smuzhiyun struct irq_desc *desc) 34*4882a593Smuzhiyun { 35*4882a593Smuzhiyun if (chip->irq_eoi) 36*4882a593Smuzhiyun chip->irq_eoi(&desc->irq_data); 37*4882a593Smuzhiyun else 38*4882a593Smuzhiyun chip->irq_unmask(&desc->irq_data); 39*4882a593Smuzhiyun } 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #endif /* __IRQCHIP_CHAINED_IRQ_H */ 42