1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) STMicroelectronics 2016 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Author: Benjamin Gaignard <benjamin.gaignard@st.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _STM32_TIMER_TRIGGER_H_ 9*4882a593Smuzhiyun #define _STM32_TIMER_TRIGGER_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define TIM1_TRGO "tim1_trgo" 12*4882a593Smuzhiyun #define TIM1_TRGO2 "tim1_trgo2" 13*4882a593Smuzhiyun #define TIM1_CH1 "tim1_ch1" 14*4882a593Smuzhiyun #define TIM1_CH2 "tim1_ch2" 15*4882a593Smuzhiyun #define TIM1_CH3 "tim1_ch3" 16*4882a593Smuzhiyun #define TIM1_CH4 "tim1_ch4" 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define TIM2_TRGO "tim2_trgo" 19*4882a593Smuzhiyun #define TIM2_CH1 "tim2_ch1" 20*4882a593Smuzhiyun #define TIM2_CH2 "tim2_ch2" 21*4882a593Smuzhiyun #define TIM2_CH3 "tim2_ch3" 22*4882a593Smuzhiyun #define TIM2_CH4 "tim2_ch4" 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #define TIM3_TRGO "tim3_trgo" 25*4882a593Smuzhiyun #define TIM3_CH1 "tim3_ch1" 26*4882a593Smuzhiyun #define TIM3_CH2 "tim3_ch2" 27*4882a593Smuzhiyun #define TIM3_CH3 "tim3_ch3" 28*4882a593Smuzhiyun #define TIM3_CH4 "tim3_ch4" 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define TIM4_TRGO "tim4_trgo" 31*4882a593Smuzhiyun #define TIM4_CH1 "tim4_ch1" 32*4882a593Smuzhiyun #define TIM4_CH2 "tim4_ch2" 33*4882a593Smuzhiyun #define TIM4_CH3 "tim4_ch3" 34*4882a593Smuzhiyun #define TIM4_CH4 "tim4_ch4" 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define TIM5_TRGO "tim5_trgo" 37*4882a593Smuzhiyun #define TIM5_CH1 "tim5_ch1" 38*4882a593Smuzhiyun #define TIM5_CH2 "tim5_ch2" 39*4882a593Smuzhiyun #define TIM5_CH3 "tim5_ch3" 40*4882a593Smuzhiyun #define TIM5_CH4 "tim5_ch4" 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun #define TIM6_TRGO "tim6_trgo" 43*4882a593Smuzhiyun 44*4882a593Smuzhiyun #define TIM7_TRGO "tim7_trgo" 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define TIM8_TRGO "tim8_trgo" 47*4882a593Smuzhiyun #define TIM8_TRGO2 "tim8_trgo2" 48*4882a593Smuzhiyun #define TIM8_CH1 "tim8_ch1" 49*4882a593Smuzhiyun #define TIM8_CH2 "tim8_ch2" 50*4882a593Smuzhiyun #define TIM8_CH3 "tim8_ch3" 51*4882a593Smuzhiyun #define TIM8_CH4 "tim8_ch4" 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define TIM9_TRGO "tim9_trgo" 54*4882a593Smuzhiyun #define TIM9_CH1 "tim9_ch1" 55*4882a593Smuzhiyun #define TIM9_CH2 "tim9_ch2" 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun #define TIM10_OC1 "tim10_oc1" 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define TIM11_OC1 "tim11_oc1" 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define TIM12_TRGO "tim12_trgo" 62*4882a593Smuzhiyun #define TIM12_CH1 "tim12_ch1" 63*4882a593Smuzhiyun #define TIM12_CH2 "tim12_ch2" 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define TIM13_OC1 "tim13_oc1" 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define TIM14_OC1 "tim14_oc1" 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define TIM15_TRGO "tim15_trgo" 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #define TIM16_OC1 "tim16_oc1" 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #define TIM17_OC1 "tim17_oc1" 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #if IS_REACHABLE(CONFIG_IIO_STM32_TIMER_TRIGGER) 76*4882a593Smuzhiyun bool is_stm32_timer_trigger(struct iio_trigger *trig); 77*4882a593Smuzhiyun #else is_stm32_timer_trigger(struct iio_trigger * trig)78*4882a593Smuzhiyunstatic inline bool is_stm32_timer_trigger(struct iio_trigger *trig) 79*4882a593Smuzhiyun { 80*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_IIO_STM32_TIMER_TRIGGER) 81*4882a593Smuzhiyun pr_warn_once("stm32-timer-trigger not linked in\n"); 82*4882a593Smuzhiyun #endif 83*4882a593Smuzhiyun return false; 84*4882a593Smuzhiyun } 85*4882a593Smuzhiyun #endif 86*4882a593Smuzhiyun #endif 87