1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Support code for Analog Devices Sigma-Delta ADCs
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2012 Analog Devices Inc.
6*4882a593Smuzhiyun * Author: Lars-Peter Clausen <lars@metafoo.de>
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun #ifndef __AD_SIGMA_DELTA_H__
9*4882a593Smuzhiyun #define __AD_SIGMA_DELTA_H__
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun enum ad_sigma_delta_mode {
12*4882a593Smuzhiyun AD_SD_MODE_CONTINUOUS = 0,
13*4882a593Smuzhiyun AD_SD_MODE_SINGLE = 1,
14*4882a593Smuzhiyun AD_SD_MODE_IDLE = 2,
15*4882a593Smuzhiyun AD_SD_MODE_POWERDOWN = 3,
16*4882a593Smuzhiyun };
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /**
19*4882a593Smuzhiyun * struct ad_sigma_delta_calib_data - Calibration data for Sigma Delta devices
20*4882a593Smuzhiyun * @mode: Calibration mode.
21*4882a593Smuzhiyun * @channel: Calibration channel.
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun struct ad_sd_calib_data {
24*4882a593Smuzhiyun unsigned int mode;
25*4882a593Smuzhiyun unsigned int channel;
26*4882a593Smuzhiyun };
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun struct ad_sigma_delta;
29*4882a593Smuzhiyun struct iio_dev;
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /**
32*4882a593Smuzhiyun * struct ad_sigma_delta_info - Sigma Delta driver specific callbacks and options
33*4882a593Smuzhiyun * @set_channel: Will be called to select the current channel, may be NULL.
34*4882a593Smuzhiyun * @set_mode: Will be called to select the current mode, may be NULL.
35*4882a593Smuzhiyun * @postprocess_sample: Is called for each sampled data word, can be used to
36*4882a593Smuzhiyun * modify or drop the sample data, it, may be NULL.
37*4882a593Smuzhiyun * @has_registers: true if the device has writable and readable registers, false
38*4882a593Smuzhiyun * if there is just one read-only sample data shift register.
39*4882a593Smuzhiyun * @addr_shift: Shift of the register address in the communications register.
40*4882a593Smuzhiyun * @read_mask: Mask for the communications register having the read bit set.
41*4882a593Smuzhiyun * @data_reg: Address of the data register, if 0 the default address of 0x3 will
42*4882a593Smuzhiyun * be used.
43*4882a593Smuzhiyun * @irq_flags: flags for the interrupt used by the triggered buffer
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun struct ad_sigma_delta_info {
46*4882a593Smuzhiyun int (*set_channel)(struct ad_sigma_delta *, unsigned int channel);
47*4882a593Smuzhiyun int (*set_mode)(struct ad_sigma_delta *, enum ad_sigma_delta_mode mode);
48*4882a593Smuzhiyun int (*postprocess_sample)(struct ad_sigma_delta *, unsigned int raw_sample);
49*4882a593Smuzhiyun bool has_registers;
50*4882a593Smuzhiyun unsigned int addr_shift;
51*4882a593Smuzhiyun unsigned int read_mask;
52*4882a593Smuzhiyun unsigned int data_reg;
53*4882a593Smuzhiyun unsigned long irq_flags;
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun /**
57*4882a593Smuzhiyun * struct ad_sigma_delta - Sigma Delta device struct
58*4882a593Smuzhiyun * @spi: The spi device associated with the Sigma Delta device.
59*4882a593Smuzhiyun * @trig: The IIO trigger associated with the Sigma Delta device.
60*4882a593Smuzhiyun *
61*4882a593Smuzhiyun * Most of the fields are private to the sigma delta library code and should not
62*4882a593Smuzhiyun * be accessed by individual drivers.
63*4882a593Smuzhiyun */
64*4882a593Smuzhiyun struct ad_sigma_delta {
65*4882a593Smuzhiyun struct spi_device *spi;
66*4882a593Smuzhiyun struct iio_trigger *trig;
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun /* private: */
69*4882a593Smuzhiyun struct completion completion;
70*4882a593Smuzhiyun bool irq_dis;
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun bool bus_locked;
73*4882a593Smuzhiyun bool keep_cs_asserted;
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun uint8_t comm;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun const struct ad_sigma_delta_info *info;
78*4882a593Smuzhiyun
79*4882a593Smuzhiyun /*
80*4882a593Smuzhiyun * DMA (thus cache coherency maintenance) requires the
81*4882a593Smuzhiyun * transfer buffers to live in their own cache lines.
82*4882a593Smuzhiyun * 'tx_buf' is up to 32 bits.
83*4882a593Smuzhiyun * 'rx_buf' is up to 32 bits per sample + 64 bit timestamp,
84*4882a593Smuzhiyun * rounded to 16 bytes to take into account padding.
85*4882a593Smuzhiyun */
86*4882a593Smuzhiyun uint8_t tx_buf[4] ____cacheline_aligned;
87*4882a593Smuzhiyun uint8_t rx_buf[16] __aligned(8);
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
ad_sigma_delta_set_channel(struct ad_sigma_delta * sd,unsigned int channel)90*4882a593Smuzhiyun static inline int ad_sigma_delta_set_channel(struct ad_sigma_delta *sd,
91*4882a593Smuzhiyun unsigned int channel)
92*4882a593Smuzhiyun {
93*4882a593Smuzhiyun if (sd->info->set_channel)
94*4882a593Smuzhiyun return sd->info->set_channel(sd, channel);
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun return 0;
97*4882a593Smuzhiyun }
98*4882a593Smuzhiyun
ad_sigma_delta_set_mode(struct ad_sigma_delta * sd,unsigned int mode)99*4882a593Smuzhiyun static inline int ad_sigma_delta_set_mode(struct ad_sigma_delta *sd,
100*4882a593Smuzhiyun unsigned int mode)
101*4882a593Smuzhiyun {
102*4882a593Smuzhiyun if (sd->info->set_mode)
103*4882a593Smuzhiyun return sd->info->set_mode(sd, mode);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return 0;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
ad_sigma_delta_postprocess_sample(struct ad_sigma_delta * sd,unsigned int raw_sample)108*4882a593Smuzhiyun static inline int ad_sigma_delta_postprocess_sample(struct ad_sigma_delta *sd,
109*4882a593Smuzhiyun unsigned int raw_sample)
110*4882a593Smuzhiyun {
111*4882a593Smuzhiyun if (sd->info->postprocess_sample)
112*4882a593Smuzhiyun return sd->info->postprocess_sample(sd, raw_sample);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun return 0;
115*4882a593Smuzhiyun }
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun void ad_sd_set_comm(struct ad_sigma_delta *sigma_delta, uint8_t comm);
118*4882a593Smuzhiyun int ad_sd_write_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg,
119*4882a593Smuzhiyun unsigned int size, unsigned int val);
120*4882a593Smuzhiyun int ad_sd_read_reg(struct ad_sigma_delta *sigma_delta, unsigned int reg,
121*4882a593Smuzhiyun unsigned int size, unsigned int *val);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun int ad_sd_reset(struct ad_sigma_delta *sigma_delta,
124*4882a593Smuzhiyun unsigned int reset_length);
125*4882a593Smuzhiyun
126*4882a593Smuzhiyun int ad_sigma_delta_single_conversion(struct iio_dev *indio_dev,
127*4882a593Smuzhiyun const struct iio_chan_spec *chan, int *val);
128*4882a593Smuzhiyun int ad_sd_calibrate(struct ad_sigma_delta *sigma_delta,
129*4882a593Smuzhiyun unsigned int mode, unsigned int channel);
130*4882a593Smuzhiyun int ad_sd_calibrate_all(struct ad_sigma_delta *sigma_delta,
131*4882a593Smuzhiyun const struct ad_sd_calib_data *cd, unsigned int n);
132*4882a593Smuzhiyun int ad_sd_init(struct ad_sigma_delta *sigma_delta, struct iio_dev *indio_dev,
133*4882a593Smuzhiyun struct spi_device *spi, const struct ad_sigma_delta_info *info);
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun int ad_sd_setup_buffer_and_trigger(struct iio_dev *indio_dev);
136*4882a593Smuzhiyun void ad_sd_cleanup_buffer_and_trigger(struct iio_dev *indio_dev);
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun int ad_sd_validate_trigger(struct iio_dev *indio_dev, struct iio_trigger *trig);
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun #endif
141