1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef __HPET__ 3*4882a593Smuzhiyun #define __HPET__ 1 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <uapi/linux/hpet.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /* 9*4882a593Smuzhiyun * Offsets into HPET Registers 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct hpet { 13*4882a593Smuzhiyun u64 hpet_cap; /* capabilities */ 14*4882a593Smuzhiyun u64 res0; /* reserved */ 15*4882a593Smuzhiyun u64 hpet_config; /* configuration */ 16*4882a593Smuzhiyun u64 res1; /* reserved */ 17*4882a593Smuzhiyun u64 hpet_isr; /* interrupt status reg */ 18*4882a593Smuzhiyun u64 res2[25]; /* reserved */ 19*4882a593Smuzhiyun union { /* main counter */ 20*4882a593Smuzhiyun u64 _hpet_mc64; 21*4882a593Smuzhiyun u32 _hpet_mc32; 22*4882a593Smuzhiyun unsigned long _hpet_mc; 23*4882a593Smuzhiyun } _u0; 24*4882a593Smuzhiyun u64 res3; /* reserved */ 25*4882a593Smuzhiyun struct hpet_timer { 26*4882a593Smuzhiyun u64 hpet_config; /* configuration/cap */ 27*4882a593Smuzhiyun union { /* timer compare register */ 28*4882a593Smuzhiyun u64 _hpet_hc64; 29*4882a593Smuzhiyun u32 _hpet_hc32; 30*4882a593Smuzhiyun unsigned long _hpet_compare; 31*4882a593Smuzhiyun } _u1; 32*4882a593Smuzhiyun u64 hpet_fsb[2]; /* FSB route */ 33*4882a593Smuzhiyun } hpet_timers[1]; 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define hpet_mc _u0._hpet_mc 37*4882a593Smuzhiyun #define hpet_compare _u1._hpet_compare 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define HPET_MAX_TIMERS (32) 40*4882a593Smuzhiyun #define HPET_MAX_IRQ (32) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* 43*4882a593Smuzhiyun * HPET general capabilities register 44*4882a593Smuzhiyun */ 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define HPET_COUNTER_CLK_PERIOD_MASK (0xffffffff00000000ULL) 47*4882a593Smuzhiyun #define HPET_COUNTER_CLK_PERIOD_SHIFT (32UL) 48*4882a593Smuzhiyun #define HPET_VENDOR_ID_MASK (0x00000000ffff0000ULL) 49*4882a593Smuzhiyun #define HPET_VENDOR_ID_SHIFT (16ULL) 50*4882a593Smuzhiyun #define HPET_LEG_RT_CAP_MASK (0x8000) 51*4882a593Smuzhiyun #define HPET_COUNTER_SIZE_MASK (0x2000) 52*4882a593Smuzhiyun #define HPET_NUM_TIM_CAP_MASK (0x1f00) 53*4882a593Smuzhiyun #define HPET_NUM_TIM_CAP_SHIFT (8ULL) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun /* 56*4882a593Smuzhiyun * HPET general configuration register 57*4882a593Smuzhiyun */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define HPET_LEG_RT_CNF_MASK (2UL) 60*4882a593Smuzhiyun #define HPET_ENABLE_CNF_MASK (1UL) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* 64*4882a593Smuzhiyun * Timer configuration register 65*4882a593Smuzhiyun */ 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define Tn_INT_ROUTE_CAP_MASK (0xffffffff00000000ULL) 68*4882a593Smuzhiyun #define Tn_INT_ROUTE_CAP_SHIFT (32UL) 69*4882a593Smuzhiyun #define Tn_FSB_INT_DELCAP_MASK (0x8000UL) 70*4882a593Smuzhiyun #define Tn_FSB_INT_DELCAP_SHIFT (15) 71*4882a593Smuzhiyun #define Tn_FSB_EN_CNF_MASK (0x4000UL) 72*4882a593Smuzhiyun #define Tn_FSB_EN_CNF_SHIFT (14) 73*4882a593Smuzhiyun #define Tn_INT_ROUTE_CNF_MASK (0x3e00UL) 74*4882a593Smuzhiyun #define Tn_INT_ROUTE_CNF_SHIFT (9) 75*4882a593Smuzhiyun #define Tn_32MODE_CNF_MASK (0x0100UL) 76*4882a593Smuzhiyun #define Tn_VAL_SET_CNF_MASK (0x0040UL) 77*4882a593Smuzhiyun #define Tn_SIZE_CAP_MASK (0x0020UL) 78*4882a593Smuzhiyun #define Tn_PER_INT_CAP_MASK (0x0010UL) 79*4882a593Smuzhiyun #define Tn_TYPE_CNF_MASK (0x0008UL) 80*4882a593Smuzhiyun #define Tn_INT_ENB_CNF_MASK (0x0004UL) 81*4882a593Smuzhiyun #define Tn_INT_TYPE_CNF_MASK (0x0002UL) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun /* 84*4882a593Smuzhiyun * Timer FSB Interrupt Route Register 85*4882a593Smuzhiyun */ 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun #define Tn_FSB_INT_ADDR_MASK (0xffffffff00000000ULL) 88*4882a593Smuzhiyun #define Tn_FSB_INT_ADDR_SHIFT (32UL) 89*4882a593Smuzhiyun #define Tn_FSB_INT_VAL_MASK (0x00000000ffffffffULL) 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun /* 92*4882a593Smuzhiyun * exported interfaces 93*4882a593Smuzhiyun */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun struct hpet_data { 96*4882a593Smuzhiyun unsigned long hd_phys_address; 97*4882a593Smuzhiyun void __iomem *hd_address; 98*4882a593Smuzhiyun unsigned short hd_nirqs; 99*4882a593Smuzhiyun unsigned int hd_state; /* timer allocated */ 100*4882a593Smuzhiyun unsigned int hd_irq[HPET_MAX_TIMERS]; 101*4882a593Smuzhiyun }; 102*4882a593Smuzhiyun hpet_reserve_timer(struct hpet_data * hd,int timer)103*4882a593Smuzhiyunstatic inline void hpet_reserve_timer(struct hpet_data *hd, int timer) 104*4882a593Smuzhiyun { 105*4882a593Smuzhiyun hd->hd_state |= (1 << timer); 106*4882a593Smuzhiyun return; 107*4882a593Smuzhiyun } 108*4882a593Smuzhiyun 109*4882a593Smuzhiyun int hpet_alloc(struct hpet_data *); 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun #endif /* !__HPET__ */ 112