1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun 3*4882a593Smuzhiyun #ifndef _LINUX_GPIO_REGMAP_H 4*4882a593Smuzhiyun #define _LINUX_GPIO_REGMAP_H 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun struct device; 7*4882a593Smuzhiyun struct gpio_regmap; 8*4882a593Smuzhiyun struct irq_domain; 9*4882a593Smuzhiyun struct regmap; 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define GPIO_REGMAP_ADDR_ZERO ((unsigned int)(-1)) 12*4882a593Smuzhiyun #define GPIO_REGMAP_ADDR(addr) ((addr) ? : GPIO_REGMAP_ADDR_ZERO) 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /** 15*4882a593Smuzhiyun * struct gpio_regmap_config - Description of a generic regmap gpio_chip. 16*4882a593Smuzhiyun * @parent: The parent device 17*4882a593Smuzhiyun * @regmap: The regmap used to access the registers 18*4882a593Smuzhiyun * given, the name of the device is used 19*4882a593Smuzhiyun * @label: (Optional) Descriptive name for GPIO controller. 20*4882a593Smuzhiyun * If not given, the name of the device is used. 21*4882a593Smuzhiyun * @ngpio: Number of GPIOs 22*4882a593Smuzhiyun * @names: (Optional) Array of names for gpios 23*4882a593Smuzhiyun * @reg_dat_base: (Optional) (in) register base address 24*4882a593Smuzhiyun * @reg_set_base: (Optional) set register base address 25*4882a593Smuzhiyun * @reg_clr_base: (Optional) clear register base address 26*4882a593Smuzhiyun * @reg_dir_in_base: (Optional) in setting register base address 27*4882a593Smuzhiyun * @reg_dir_out_base: (Optional) out setting register base address 28*4882a593Smuzhiyun * @reg_stride: (Optional) May be set if the registers (of the 29*4882a593Smuzhiyun * same type, dat, set, etc) are not consecutive. 30*4882a593Smuzhiyun * @ngpio_per_reg: Number of GPIOs per register 31*4882a593Smuzhiyun * @irq_domain: (Optional) IRQ domain if the controller is 32*4882a593Smuzhiyun * interrupt-capable 33*4882a593Smuzhiyun * @reg_mask_xlate: (Optional) Translates base address and GPIO 34*4882a593Smuzhiyun * offset to a register/bitmask pair. If not 35*4882a593Smuzhiyun * given the default gpio_regmap_simple_xlate() 36*4882a593Smuzhiyun * is used. 37*4882a593Smuzhiyun * 38*4882a593Smuzhiyun * The ->reg_mask_xlate translates a given base address and GPIO offset to 39*4882a593Smuzhiyun * register and mask pair. The base address is one of the given register 40*4882a593Smuzhiyun * base addresses in this structure. 41*4882a593Smuzhiyun * 42*4882a593Smuzhiyun * Although all register base addresses are marked as optional, there are 43*4882a593Smuzhiyun * several rules: 44*4882a593Smuzhiyun * 1. if you only have @reg_dat_base set, then it is input-only 45*4882a593Smuzhiyun * 2. if you only have @reg_set_base set, then it is output-only 46*4882a593Smuzhiyun * 3. if you have either @reg_dir_in_base or @reg_dir_out_base set, then 47*4882a593Smuzhiyun * you have to set both @reg_dat_base and @reg_set_base 48*4882a593Smuzhiyun * 4. if you have @reg_set_base set, you may also set @reg_clr_base to have 49*4882a593Smuzhiyun * two different registers for setting and clearing the output. This is 50*4882a593Smuzhiyun * also valid for the output-only case. 51*4882a593Smuzhiyun * 5. @reg_dir_in_base and @reg_dir_out_base are exclusive; is there really 52*4882a593Smuzhiyun * hardware which has redundant registers? 53*4882a593Smuzhiyun * 54*4882a593Smuzhiyun * Note: All base addresses may have the special value %GPIO_REGMAP_ADDR_ZERO 55*4882a593Smuzhiyun * which forces the address to the value 0. 56*4882a593Smuzhiyun */ 57*4882a593Smuzhiyun struct gpio_regmap_config { 58*4882a593Smuzhiyun struct device *parent; 59*4882a593Smuzhiyun struct regmap *regmap; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun const char *label; 62*4882a593Smuzhiyun int ngpio; 63*4882a593Smuzhiyun const char *const *names; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun unsigned int reg_dat_base; 66*4882a593Smuzhiyun unsigned int reg_set_base; 67*4882a593Smuzhiyun unsigned int reg_clr_base; 68*4882a593Smuzhiyun unsigned int reg_dir_in_base; 69*4882a593Smuzhiyun unsigned int reg_dir_out_base; 70*4882a593Smuzhiyun int reg_stride; 71*4882a593Smuzhiyun int ngpio_per_reg; 72*4882a593Smuzhiyun struct irq_domain *irq_domain; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun int (*reg_mask_xlate)(struct gpio_regmap *gpio, unsigned int base, 75*4882a593Smuzhiyun unsigned int offset, unsigned int *reg, 76*4882a593Smuzhiyun unsigned int *mask); 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun struct gpio_regmap *gpio_regmap_register(const struct gpio_regmap_config *config); 80*4882a593Smuzhiyun void gpio_regmap_unregister(struct gpio_regmap *gpio); 81*4882a593Smuzhiyun struct gpio_regmap *devm_gpio_regmap_register(struct device *dev, 82*4882a593Smuzhiyun const struct gpio_regmap_config *config); 83*4882a593Smuzhiyun void gpio_regmap_set_drvdata(struct gpio_regmap *gpio, void *data); 84*4882a593Smuzhiyun void *gpio_regmap_get_drvdata(struct gpio_regmap *gpio); 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif /* _LINUX_GPIO_REGMAP_H */ 87