1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * include/linux/fsl_devices.h
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Definitions for any platform device related flags or structures for
6*4882a593Smuzhiyun * Freescale processor devices
7*4882a593Smuzhiyun *
8*4882a593Smuzhiyun * Maintainer: Kumar Gala <galak@kernel.crashing.org>
9*4882a593Smuzhiyun *
10*4882a593Smuzhiyun * Copyright 2004,2012 Freescale Semiconductor, Inc
11*4882a593Smuzhiyun */
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun #ifndef _FSL_DEVICE_H_
14*4882a593Smuzhiyun #define _FSL_DEVICE_H_
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun #define FSL_UTMI_PHY_DLY 10 /*As per P1010RM, delay for UTMI
17*4882a593Smuzhiyun PHY CLK to become stable - 10ms*/
18*4882a593Smuzhiyun #define FSL_USB_PHY_CLK_TIMEOUT 10000 /* uSec */
19*4882a593Smuzhiyun
20*4882a593Smuzhiyun #include <linux/types.h>
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /*
23*4882a593Smuzhiyun * Some conventions on how we handle peripherals on Freescale chips
24*4882a593Smuzhiyun *
25*4882a593Smuzhiyun * unique device: a platform_device entry in fsl_plat_devs[] plus
26*4882a593Smuzhiyun * associated device information in its platform_data structure.
27*4882a593Smuzhiyun *
28*4882a593Smuzhiyun * A chip is described by a set of unique devices.
29*4882a593Smuzhiyun *
30*4882a593Smuzhiyun * Each sub-arch has its own master list of unique devices and
31*4882a593Smuzhiyun * enumerates them by enum fsl_devices in a sub-arch specific header
32*4882a593Smuzhiyun *
33*4882a593Smuzhiyun * The platform data structure is broken into two parts. The
34*4882a593Smuzhiyun * first is device specific information that help identify any
35*4882a593Smuzhiyun * unique features of a peripheral. The second is any
36*4882a593Smuzhiyun * information that may be defined by the board or how the device
37*4882a593Smuzhiyun * is connected externally of the chip.
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun * naming conventions:
40*4882a593Smuzhiyun * - platform data structures: <driver>_platform_data
41*4882a593Smuzhiyun * - platform data device flags: FSL_<driver>_DEV_<FLAG>
42*4882a593Smuzhiyun * - platform data board flags: FSL_<driver>_BRD_<FLAG>
43*4882a593Smuzhiyun *
44*4882a593Smuzhiyun */
45*4882a593Smuzhiyun
46*4882a593Smuzhiyun enum fsl_usb2_controller_ver {
47*4882a593Smuzhiyun FSL_USB_VER_NONE = -1,
48*4882a593Smuzhiyun FSL_USB_VER_OLD = 0,
49*4882a593Smuzhiyun FSL_USB_VER_1_6 = 1,
50*4882a593Smuzhiyun FSL_USB_VER_2_2 = 2,
51*4882a593Smuzhiyun FSL_USB_VER_2_4 = 3,
52*4882a593Smuzhiyun FSL_USB_VER_2_5 = 4,
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun enum fsl_usb2_operating_modes {
56*4882a593Smuzhiyun FSL_USB2_MPH_HOST,
57*4882a593Smuzhiyun FSL_USB2_DR_HOST,
58*4882a593Smuzhiyun FSL_USB2_DR_DEVICE,
59*4882a593Smuzhiyun FSL_USB2_DR_OTG,
60*4882a593Smuzhiyun };
61*4882a593Smuzhiyun
62*4882a593Smuzhiyun enum fsl_usb2_phy_modes {
63*4882a593Smuzhiyun FSL_USB2_PHY_NONE,
64*4882a593Smuzhiyun FSL_USB2_PHY_ULPI,
65*4882a593Smuzhiyun FSL_USB2_PHY_UTMI,
66*4882a593Smuzhiyun FSL_USB2_PHY_UTMI_WIDE,
67*4882a593Smuzhiyun FSL_USB2_PHY_SERIAL,
68*4882a593Smuzhiyun FSL_USB2_PHY_UTMI_DUAL,
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun
71*4882a593Smuzhiyun struct clk;
72*4882a593Smuzhiyun struct platform_device;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct fsl_usb2_platform_data {
75*4882a593Smuzhiyun /* board specific information */
76*4882a593Smuzhiyun enum fsl_usb2_controller_ver controller_ver;
77*4882a593Smuzhiyun enum fsl_usb2_operating_modes operating_mode;
78*4882a593Smuzhiyun enum fsl_usb2_phy_modes phy_mode;
79*4882a593Smuzhiyun unsigned int port_enables;
80*4882a593Smuzhiyun unsigned int workaround;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun int (*init)(struct platform_device *);
83*4882a593Smuzhiyun void (*exit)(struct platform_device *);
84*4882a593Smuzhiyun void __iomem *regs; /* ioremap'd register base */
85*4882a593Smuzhiyun struct clk *clk;
86*4882a593Smuzhiyun unsigned power_budget; /* hcd->power_budget */
87*4882a593Smuzhiyun unsigned big_endian_mmio:1;
88*4882a593Smuzhiyun unsigned big_endian_desc:1;
89*4882a593Smuzhiyun unsigned es:1; /* need USBMODE:ES */
90*4882a593Smuzhiyun unsigned le_setup_buf:1;
91*4882a593Smuzhiyun unsigned have_sysif_regs:1;
92*4882a593Smuzhiyun unsigned invert_drvvbus:1;
93*4882a593Smuzhiyun unsigned invert_pwr_fault:1;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun unsigned suspended:1;
96*4882a593Smuzhiyun unsigned already_suspended:1;
97*4882a593Smuzhiyun unsigned has_fsl_erratum_a007792:1;
98*4882a593Smuzhiyun unsigned has_fsl_erratum_14:1;
99*4882a593Smuzhiyun unsigned has_fsl_erratum_a005275:1;
100*4882a593Smuzhiyun unsigned has_fsl_erratum_a005697:1;
101*4882a593Smuzhiyun unsigned has_fsl_erratum_a006918:1;
102*4882a593Smuzhiyun unsigned check_phy_clk_valid:1;
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* register save area for suspend/resume */
105*4882a593Smuzhiyun u32 pm_command;
106*4882a593Smuzhiyun u32 pm_status;
107*4882a593Smuzhiyun u32 pm_intr_enable;
108*4882a593Smuzhiyun u32 pm_frame_index;
109*4882a593Smuzhiyun u32 pm_segment;
110*4882a593Smuzhiyun u32 pm_frame_list;
111*4882a593Smuzhiyun u32 pm_async_next;
112*4882a593Smuzhiyun u32 pm_configured_flag;
113*4882a593Smuzhiyun u32 pm_portsc;
114*4882a593Smuzhiyun u32 pm_usbgenctrl;
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun /* Flags in fsl_usb2_mph_platform_data */
118*4882a593Smuzhiyun #define FSL_USB2_PORT0_ENABLED 0x00000001
119*4882a593Smuzhiyun #define FSL_USB2_PORT1_ENABLED 0x00000002
120*4882a593Smuzhiyun
121*4882a593Smuzhiyun #define FLS_USB2_WORKAROUND_ENGCM09152 (1 << 0)
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun struct spi_device;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun struct fsl_spi_platform_data {
126*4882a593Smuzhiyun u32 initial_spmode; /* initial SPMODE value */
127*4882a593Smuzhiyun s16 bus_num;
128*4882a593Smuzhiyun unsigned int flags;
129*4882a593Smuzhiyun #define SPI_QE_CPU_MODE (1 << 0) /* QE CPU ("PIO") mode */
130*4882a593Smuzhiyun #define SPI_CPM_MODE (1 << 1) /* CPM/QE ("DMA") mode */
131*4882a593Smuzhiyun #define SPI_CPM1 (1 << 2) /* SPI unit is in CPM1 block */
132*4882a593Smuzhiyun #define SPI_CPM2 (1 << 3) /* SPI unit is in CPM2 block */
133*4882a593Smuzhiyun #define SPI_QE (1 << 4) /* SPI unit is in QE block */
134*4882a593Smuzhiyun /* board specific information */
135*4882a593Smuzhiyun u16 max_chipselect;
136*4882a593Smuzhiyun void (*cs_control)(struct spi_device *spi, bool on);
137*4882a593Smuzhiyun u32 sysclk;
138*4882a593Smuzhiyun };
139*4882a593Smuzhiyun
140*4882a593Smuzhiyun struct mpc8xx_pcmcia_ops {
141*4882a593Smuzhiyun void(*hw_ctrl)(int slot, int enable);
142*4882a593Smuzhiyun int(*voltage_set)(int slot, int vcc, int vpp);
143*4882a593Smuzhiyun };
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun /* Returns non-zero if the current suspend operation would
146*4882a593Smuzhiyun * lead to a deep sleep (i.e. power removed from the core,
147*4882a593Smuzhiyun * instead of just the clock).
148*4882a593Smuzhiyun */
149*4882a593Smuzhiyun #if defined(CONFIG_PPC_83xx) && defined(CONFIG_SUSPEND)
150*4882a593Smuzhiyun int fsl_deep_sleep(void);
151*4882a593Smuzhiyun #else
fsl_deep_sleep(void)152*4882a593Smuzhiyun static inline int fsl_deep_sleep(void) { return 0; }
153*4882a593Smuzhiyun #endif
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun #endif /* _FSL_DEVICE_H_ */
156