1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0 2*4882a593Smuzhiyun #ifndef __FSL_FTM_H__ 3*4882a593Smuzhiyun #define __FSL_FTM_H__ 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #define FTM_SC 0x0 /* Status And Control */ 6*4882a593Smuzhiyun #define FTM_CNT 0x4 /* Counter */ 7*4882a593Smuzhiyun #define FTM_MOD 0x8 /* Modulo */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #define FTM_CNTIN 0x4C /* Counter Initial Value */ 10*4882a593Smuzhiyun #define FTM_STATUS 0x50 /* Capture And Compare Status */ 11*4882a593Smuzhiyun #define FTM_MODE 0x54 /* Features Mode Selection */ 12*4882a593Smuzhiyun #define FTM_SYNC 0x58 /* Synchronization */ 13*4882a593Smuzhiyun #define FTM_OUTINIT 0x5C /* Initial State For Channels Output */ 14*4882a593Smuzhiyun #define FTM_OUTMASK 0x60 /* Output Mask */ 15*4882a593Smuzhiyun #define FTM_COMBINE 0x64 /* Function For Linked Channels */ 16*4882a593Smuzhiyun #define FTM_DEADTIME 0x68 /* Deadtime Insertion Control */ 17*4882a593Smuzhiyun #define FTM_EXTTRIG 0x6C /* FTM External Trigger */ 18*4882a593Smuzhiyun #define FTM_POL 0x70 /* Channels Polarity */ 19*4882a593Smuzhiyun #define FTM_FMS 0x74 /* Fault Mode Status */ 20*4882a593Smuzhiyun #define FTM_FILTER 0x78 /* Input Capture Filter Control */ 21*4882a593Smuzhiyun #define FTM_FLTCTRL 0x7C /* Fault Control */ 22*4882a593Smuzhiyun #define FTM_QDCTRL 0x80 /* Quadrature Decoder Control And Status */ 23*4882a593Smuzhiyun #define FTM_CONF 0x84 /* Configuration */ 24*4882a593Smuzhiyun #define FTM_FLTPOL 0x88 /* FTM Fault Input Polarity */ 25*4882a593Smuzhiyun #define FTM_SYNCONF 0x8C /* Synchronization Configuration */ 26*4882a593Smuzhiyun #define FTM_INVCTRL 0x90 /* FTM Inverting Control */ 27*4882a593Smuzhiyun #define FTM_SWOCTRL 0x94 /* FTM Software Output Control */ 28*4882a593Smuzhiyun #define FTM_PWMLOAD 0x98 /* FTM PWM Load */ 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define FTM_SC_CLK_MASK_SHIFT 3 31*4882a593Smuzhiyun #define FTM_SC_CLK_MASK (3 << FTM_SC_CLK_MASK_SHIFT) 32*4882a593Smuzhiyun #define FTM_SC_TOF 0x80 33*4882a593Smuzhiyun #define FTM_SC_TOIE 0x40 34*4882a593Smuzhiyun #define FTM_SC_CPWMS 0x20 35*4882a593Smuzhiyun #define FTM_SC_CLKS 0x18 36*4882a593Smuzhiyun #define FTM_SC_PS_1 0x0 37*4882a593Smuzhiyun #define FTM_SC_PS_2 0x1 38*4882a593Smuzhiyun #define FTM_SC_PS_4 0x2 39*4882a593Smuzhiyun #define FTM_SC_PS_8 0x3 40*4882a593Smuzhiyun #define FTM_SC_PS_16 0x4 41*4882a593Smuzhiyun #define FTM_SC_PS_32 0x5 42*4882a593Smuzhiyun #define FTM_SC_PS_64 0x6 43*4882a593Smuzhiyun #define FTM_SC_PS_128 0x7 44*4882a593Smuzhiyun #define FTM_SC_PS_MASK 0x7 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun #define FTM_MODE_FAULTIE 0x80 47*4882a593Smuzhiyun #define FTM_MODE_FAULTM 0x60 48*4882a593Smuzhiyun #define FTM_MODE_CAPTEST 0x10 49*4882a593Smuzhiyun #define FTM_MODE_PWMSYNC 0x8 50*4882a593Smuzhiyun #define FTM_MODE_WPDIS 0x4 51*4882a593Smuzhiyun #define FTM_MODE_INIT 0x2 52*4882a593Smuzhiyun #define FTM_MODE_FTMEN 0x1 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* NXP Errata: The PHAFLTREN and PHBFLTREN bits are tide to zero internally 55*4882a593Smuzhiyun * and these bits cannot be set. Flextimer cannot use Filter in 56*4882a593Smuzhiyun * Quadrature Decoder Mode. 57*4882a593Smuzhiyun * https://community.nxp.com/thread/467648#comment-1010319 58*4882a593Smuzhiyun */ 59*4882a593Smuzhiyun #define FTM_QDCTRL_PHAFLTREN 0x80 60*4882a593Smuzhiyun #define FTM_QDCTRL_PHBFLTREN 0x40 61*4882a593Smuzhiyun #define FTM_QDCTRL_PHAPOL 0x20 62*4882a593Smuzhiyun #define FTM_QDCTRL_PHBPOL 0x10 63*4882a593Smuzhiyun #define FTM_QDCTRL_QUADMODE 0x8 64*4882a593Smuzhiyun #define FTM_QDCTRL_QUADDIR 0x4 65*4882a593Smuzhiyun #define FTM_QDCTRL_TOFDIR 0x2 66*4882a593Smuzhiyun #define FTM_QDCTRL_QUADEN 0x1 67*4882a593Smuzhiyun 68*4882a593Smuzhiyun #define FTM_FMS_FAULTF 0x80 69*4882a593Smuzhiyun #define FTM_FMS_WPEN 0x40 70*4882a593Smuzhiyun #define FTM_FMS_FAULTIN 0x10 71*4882a593Smuzhiyun #define FTM_FMS_FAULTF3 0x8 72*4882a593Smuzhiyun #define FTM_FMS_FAULTF2 0x4 73*4882a593Smuzhiyun #define FTM_FMS_FAULTF1 0x2 74*4882a593Smuzhiyun #define FTM_FMS_FAULTF0 0x1 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define FTM_CSC_BASE 0xC 77*4882a593Smuzhiyun #define FTM_CSC_MSB 0x20 78*4882a593Smuzhiyun #define FTM_CSC_MSA 0x10 79*4882a593Smuzhiyun #define FTM_CSC_ELSB 0x8 80*4882a593Smuzhiyun #define FTM_CSC_ELSA 0x4 81*4882a593Smuzhiyun #define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8)) 82*4882a593Smuzhiyun 83*4882a593Smuzhiyun #define FTM_CV_BASE 0x10 84*4882a593Smuzhiyun #define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8)) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define FTM_PS_MAX 7 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif 89