1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Analog Devices AXI common registers & definitions 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright 2019 Analog Devices Inc. 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * https://wiki.analog.com/resources/fpga/docs/axi_ip 8*4882a593Smuzhiyun * https://wiki.analog.com/resources/fpga/docs/hdl/regmap 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #ifndef ADI_AXI_COMMON_H_ 12*4882a593Smuzhiyun #define ADI_AXI_COMMON_H_ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #define ADI_AXI_REG_VERSION 0x0000 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define ADI_AXI_PCORE_VER(major, minor, patch) \ 17*4882a593Smuzhiyun (((major) << 16) | ((minor) << 8) | (patch)) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define ADI_AXI_PCORE_VER_MAJOR(version) (((version) >> 16) & 0xff) 20*4882a593Smuzhiyun #define ADI_AXI_PCORE_VER_MINOR(version) (((version) >> 8) & 0xff) 21*4882a593Smuzhiyun #define ADI_AXI_PCORE_VER_PATCH(version) ((version) & 0xff) 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #endif /* ADI_AXI_COMMON_H_ */ 24