1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2017-2018 NXP 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Header file containing the public API for the System Controller (SC) 7*4882a593Smuzhiyun * Power Management (PM) function. This includes functions for power state 8*4882a593Smuzhiyun * control, clock control, reset control, and wake-up event control. 9*4882a593Smuzhiyun * 10*4882a593Smuzhiyun * PM_SVC (SVC) Power Management Service 11*4882a593Smuzhiyun * 12*4882a593Smuzhiyun * Module for the Power Management (PM) service. 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #ifndef _SC_PM_API_H 16*4882a593Smuzhiyun #define _SC_PM_API_H 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #include <linux/firmware/imx/sci.h> 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun /* 21*4882a593Smuzhiyun * This type is used to indicate RPC PM function calls. 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun enum imx_sc_pm_func { 24*4882a593Smuzhiyun IMX_SC_PM_FUNC_UNKNOWN = 0, 25*4882a593Smuzhiyun IMX_SC_PM_FUNC_SET_SYS_POWER_MODE = 19, 26*4882a593Smuzhiyun IMX_SC_PM_FUNC_SET_PARTITION_POWER_MODE = 1, 27*4882a593Smuzhiyun IMX_SC_PM_FUNC_GET_SYS_POWER_MODE = 2, 28*4882a593Smuzhiyun IMX_SC_PM_FUNC_SET_RESOURCE_POWER_MODE = 3, 29*4882a593Smuzhiyun IMX_SC_PM_FUNC_GET_RESOURCE_POWER_MODE = 4, 30*4882a593Smuzhiyun IMX_SC_PM_FUNC_REQ_LOW_POWER_MODE = 16, 31*4882a593Smuzhiyun IMX_SC_PM_FUNC_SET_CPU_RESUME_ADDR = 17, 32*4882a593Smuzhiyun IMX_SC_PM_FUNC_REQ_SYS_IF_POWER_MODE = 18, 33*4882a593Smuzhiyun IMX_SC_PM_FUNC_SET_CLOCK_RATE = 5, 34*4882a593Smuzhiyun IMX_SC_PM_FUNC_GET_CLOCK_RATE = 6, 35*4882a593Smuzhiyun IMX_SC_PM_FUNC_CLOCK_ENABLE = 7, 36*4882a593Smuzhiyun IMX_SC_PM_FUNC_SET_CLOCK_PARENT = 14, 37*4882a593Smuzhiyun IMX_SC_PM_FUNC_GET_CLOCK_PARENT = 15, 38*4882a593Smuzhiyun IMX_SC_PM_FUNC_RESET = 13, 39*4882a593Smuzhiyun IMX_SC_PM_FUNC_RESET_REASON = 10, 40*4882a593Smuzhiyun IMX_SC_PM_FUNC_BOOT = 8, 41*4882a593Smuzhiyun IMX_SC_PM_FUNC_REBOOT = 9, 42*4882a593Smuzhiyun IMX_SC_PM_FUNC_REBOOT_PARTITION = 12, 43*4882a593Smuzhiyun IMX_SC_PM_FUNC_CPU_START = 11, 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * Defines for ALL parameters 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun #define IMX_SC_PM_CLK_ALL UINT8_MAX /* All clocks */ 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* 52*4882a593Smuzhiyun * Defines for SC PM Power Mode 53*4882a593Smuzhiyun */ 54*4882a593Smuzhiyun #define IMX_SC_PM_PW_MODE_OFF 0 /* Power off */ 55*4882a593Smuzhiyun #define IMX_SC_PM_PW_MODE_STBY 1 /* Power in standby */ 56*4882a593Smuzhiyun #define IMX_SC_PM_PW_MODE_LP 2 /* Power in low-power */ 57*4882a593Smuzhiyun #define IMX_SC_PM_PW_MODE_ON 3 /* Power on */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 60*4882a593Smuzhiyun * Defines for SC PM CLK 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */ 63*4882a593Smuzhiyun #define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */ 64*4882a593Smuzhiyun #define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */ 65*4882a593Smuzhiyun #define IMX_SC_PM_CLK_PHY 3 /* Phy clock */ 66*4882a593Smuzhiyun #define IMX_SC_PM_CLK_MISC 4 /* Misc clock */ 67*4882a593Smuzhiyun #define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */ 68*4882a593Smuzhiyun #define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */ 69*4882a593Smuzhiyun #define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */ 70*4882a593Smuzhiyun #define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */ 71*4882a593Smuzhiyun #define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */ 72*4882a593Smuzhiyun #define IMX_SC_PM_CLK_CPU 2 /* CPU clock */ 73*4882a593Smuzhiyun #define IMX_SC_PM_CLK_PLL 4 /* PLL */ 74*4882a593Smuzhiyun #define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun /* 77*4882a593Smuzhiyun * Defines for SC PM CLK Parent 78*4882a593Smuzhiyun */ 79*4882a593Smuzhiyun #define IMX_SC_PM_PARENT_XTAL 0 /* Parent is XTAL. */ 80*4882a593Smuzhiyun #define IMX_SC_PM_PARENT_PLL0 1 /* Parent is PLL0 */ 81*4882a593Smuzhiyun #define IMX_SC_PM_PARENT_PLL1 2 /* Parent is PLL1 or PLL0/2 */ 82*4882a593Smuzhiyun #define IMX_SC_PM_PARENT_PLL2 3 /* Parent in PLL2 or PLL0/4 */ 83*4882a593Smuzhiyun #define IMX_SC_PM_PARENT_BYPS 4 /* Parent is a bypass clock. */ 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun #endif /* _SC_PM_API_H */ 86