1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2016 Freescale Semiconductor, Inc. 4*4882a593Smuzhiyun * Copyright 2017~2018 NXP 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Header file containing the public API for the System Controller (SC) 7*4882a593Smuzhiyun * Miscellaneous (MISC) function. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * MISC_SVC (SVC) Miscellaneous Service 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * Module for the Miscellaneous (MISC) service. 12*4882a593Smuzhiyun */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun #ifndef _SC_MISC_API_H 15*4882a593Smuzhiyun #define _SC_MISC_API_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun #include <linux/firmware/imx/sci.h> 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* 20*4882a593Smuzhiyun * This type is used to indicate RPC MISC function calls. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun enum imx_misc_func { 23*4882a593Smuzhiyun IMX_SC_MISC_FUNC_UNKNOWN = 0, 24*4882a593Smuzhiyun IMX_SC_MISC_FUNC_SET_CONTROL = 1, 25*4882a593Smuzhiyun IMX_SC_MISC_FUNC_GET_CONTROL = 2, 26*4882a593Smuzhiyun IMX_SC_MISC_FUNC_SET_MAX_DMA_GROUP = 4, 27*4882a593Smuzhiyun IMX_SC_MISC_FUNC_SET_DMA_GROUP = 5, 28*4882a593Smuzhiyun IMX_SC_MISC_FUNC_SECO_IMAGE_LOAD = 8, 29*4882a593Smuzhiyun IMX_SC_MISC_FUNC_SECO_AUTHENTICATE = 9, 30*4882a593Smuzhiyun IMX_SC_MISC_FUNC_DEBUG_OUT = 10, 31*4882a593Smuzhiyun IMX_SC_MISC_FUNC_WAVEFORM_CAPTURE = 6, 32*4882a593Smuzhiyun IMX_SC_MISC_FUNC_BUILD_INFO = 15, 33*4882a593Smuzhiyun IMX_SC_MISC_FUNC_UNIQUE_ID = 19, 34*4882a593Smuzhiyun IMX_SC_MISC_FUNC_SET_ARI = 3, 35*4882a593Smuzhiyun IMX_SC_MISC_FUNC_BOOT_STATUS = 7, 36*4882a593Smuzhiyun IMX_SC_MISC_FUNC_BOOT_DONE = 14, 37*4882a593Smuzhiyun IMX_SC_MISC_FUNC_OTP_FUSE_READ = 11, 38*4882a593Smuzhiyun IMX_SC_MISC_FUNC_OTP_FUSE_WRITE = 17, 39*4882a593Smuzhiyun IMX_SC_MISC_FUNC_SET_TEMP = 12, 40*4882a593Smuzhiyun IMX_SC_MISC_FUNC_GET_TEMP = 13, 41*4882a593Smuzhiyun IMX_SC_MISC_FUNC_GET_BOOT_DEV = 16, 42*4882a593Smuzhiyun IMX_SC_MISC_FUNC_GET_BUTTON_STATUS = 18, 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* 46*4882a593Smuzhiyun * Control Functions 47*4882a593Smuzhiyun */ 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun int imx_sc_misc_set_control(struct imx_sc_ipc *ipc, u32 resource, 50*4882a593Smuzhiyun u8 ctrl, u32 val); 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun int imx_sc_misc_get_control(struct imx_sc_ipc *ipc, u32 resource, 53*4882a593Smuzhiyun u8 ctrl, u32 *val); 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun int imx_sc_pm_cpu_start(struct imx_sc_ipc *ipc, u32 resource, 56*4882a593Smuzhiyun bool enable, u64 phys_addr); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif /* _SC_MISC_API_H */ 59