1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2008 4*4882a593Smuzhiyun * Guennadi Liakhovetski, DENX Software Engineering, <lg@denx.de> 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (C) 2005-2007 Freescale Semiconductor, Inc. 7*4882a593Smuzhiyun */ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #ifndef __LINUX_DMA_IPU_DMA_H 10*4882a593Smuzhiyun #define __LINUX_DMA_IPU_DMA_H 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #include <linux/types.h> 13*4882a593Smuzhiyun #include <linux/dmaengine.h> 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* IPU DMA Controller channel definitions. */ 16*4882a593Smuzhiyun enum ipu_channel { 17*4882a593Smuzhiyun IDMAC_IC_0 = 0, /* IC (encoding task) to memory */ 18*4882a593Smuzhiyun IDMAC_IC_1 = 1, /* IC (viewfinder task) to memory */ 19*4882a593Smuzhiyun IDMAC_ADC_0 = 1, 20*4882a593Smuzhiyun IDMAC_IC_2 = 2, 21*4882a593Smuzhiyun IDMAC_ADC_1 = 2, 22*4882a593Smuzhiyun IDMAC_IC_3 = 3, 23*4882a593Smuzhiyun IDMAC_IC_4 = 4, 24*4882a593Smuzhiyun IDMAC_IC_5 = 5, 25*4882a593Smuzhiyun IDMAC_IC_6 = 6, 26*4882a593Smuzhiyun IDMAC_IC_7 = 7, /* IC (sensor data) to memory */ 27*4882a593Smuzhiyun IDMAC_IC_8 = 8, 28*4882a593Smuzhiyun IDMAC_IC_9 = 9, 29*4882a593Smuzhiyun IDMAC_IC_10 = 10, 30*4882a593Smuzhiyun IDMAC_IC_11 = 11, 31*4882a593Smuzhiyun IDMAC_IC_12 = 12, 32*4882a593Smuzhiyun IDMAC_IC_13 = 13, 33*4882a593Smuzhiyun IDMAC_SDC_0 = 14, /* Background synchronous display data */ 34*4882a593Smuzhiyun IDMAC_SDC_1 = 15, /* Foreground data (overlay) */ 35*4882a593Smuzhiyun IDMAC_SDC_2 = 16, 36*4882a593Smuzhiyun IDMAC_SDC_3 = 17, 37*4882a593Smuzhiyun IDMAC_ADC_2 = 18, 38*4882a593Smuzhiyun IDMAC_ADC_3 = 19, 39*4882a593Smuzhiyun IDMAC_ADC_4 = 20, 40*4882a593Smuzhiyun IDMAC_ADC_5 = 21, 41*4882a593Smuzhiyun IDMAC_ADC_6 = 22, 42*4882a593Smuzhiyun IDMAC_ADC_7 = 23, 43*4882a593Smuzhiyun IDMAC_PF_0 = 24, 44*4882a593Smuzhiyun IDMAC_PF_1 = 25, 45*4882a593Smuzhiyun IDMAC_PF_2 = 26, 46*4882a593Smuzhiyun IDMAC_PF_3 = 27, 47*4882a593Smuzhiyun IDMAC_PF_4 = 28, 48*4882a593Smuzhiyun IDMAC_PF_5 = 29, 49*4882a593Smuzhiyun IDMAC_PF_6 = 30, 50*4882a593Smuzhiyun IDMAC_PF_7 = 31, 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* Order significant! */ 54*4882a593Smuzhiyun enum ipu_channel_status { 55*4882a593Smuzhiyun IPU_CHANNEL_FREE, 56*4882a593Smuzhiyun IPU_CHANNEL_INITIALIZED, 57*4882a593Smuzhiyun IPU_CHANNEL_READY, 58*4882a593Smuzhiyun IPU_CHANNEL_ENABLED, 59*4882a593Smuzhiyun }; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define IPU_CHANNELS_NUM 32 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun enum pixel_fmt { 64*4882a593Smuzhiyun /* 1 byte */ 65*4882a593Smuzhiyun IPU_PIX_FMT_GENERIC, 66*4882a593Smuzhiyun IPU_PIX_FMT_RGB332, 67*4882a593Smuzhiyun IPU_PIX_FMT_YUV420P, 68*4882a593Smuzhiyun IPU_PIX_FMT_YUV422P, 69*4882a593Smuzhiyun IPU_PIX_FMT_YUV420P2, 70*4882a593Smuzhiyun IPU_PIX_FMT_YVU422P, 71*4882a593Smuzhiyun /* 2 bytes */ 72*4882a593Smuzhiyun IPU_PIX_FMT_RGB565, 73*4882a593Smuzhiyun IPU_PIX_FMT_RGB666, 74*4882a593Smuzhiyun IPU_PIX_FMT_BGR666, 75*4882a593Smuzhiyun IPU_PIX_FMT_YUYV, 76*4882a593Smuzhiyun IPU_PIX_FMT_UYVY, 77*4882a593Smuzhiyun /* 3 bytes */ 78*4882a593Smuzhiyun IPU_PIX_FMT_RGB24, 79*4882a593Smuzhiyun IPU_PIX_FMT_BGR24, 80*4882a593Smuzhiyun /* 4 bytes */ 81*4882a593Smuzhiyun IPU_PIX_FMT_GENERIC_32, 82*4882a593Smuzhiyun IPU_PIX_FMT_RGB32, 83*4882a593Smuzhiyun IPU_PIX_FMT_BGR32, 84*4882a593Smuzhiyun IPU_PIX_FMT_ABGR32, 85*4882a593Smuzhiyun IPU_PIX_FMT_BGRA32, 86*4882a593Smuzhiyun IPU_PIX_FMT_RGBA32, 87*4882a593Smuzhiyun }; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun enum ipu_color_space { 90*4882a593Smuzhiyun IPU_COLORSPACE_RGB, 91*4882a593Smuzhiyun IPU_COLORSPACE_YCBCR, 92*4882a593Smuzhiyun IPU_COLORSPACE_YUV 93*4882a593Smuzhiyun }; 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun /* 96*4882a593Smuzhiyun * Enumeration of IPU rotation modes 97*4882a593Smuzhiyun */ 98*4882a593Smuzhiyun enum ipu_rotate_mode { 99*4882a593Smuzhiyun /* Note the enum values correspond to BAM value */ 100*4882a593Smuzhiyun IPU_ROTATE_NONE = 0, 101*4882a593Smuzhiyun IPU_ROTATE_VERT_FLIP = 1, 102*4882a593Smuzhiyun IPU_ROTATE_HORIZ_FLIP = 2, 103*4882a593Smuzhiyun IPU_ROTATE_180 = 3, 104*4882a593Smuzhiyun IPU_ROTATE_90_RIGHT = 4, 105*4882a593Smuzhiyun IPU_ROTATE_90_RIGHT_VFLIP = 5, 106*4882a593Smuzhiyun IPU_ROTATE_90_RIGHT_HFLIP = 6, 107*4882a593Smuzhiyun IPU_ROTATE_90_LEFT = 7, 108*4882a593Smuzhiyun }; 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* 111*4882a593Smuzhiyun * Enumeration of DI ports for ADC. 112*4882a593Smuzhiyun */ 113*4882a593Smuzhiyun enum display_port { 114*4882a593Smuzhiyun DISP0, 115*4882a593Smuzhiyun DISP1, 116*4882a593Smuzhiyun DISP2, 117*4882a593Smuzhiyun DISP3 118*4882a593Smuzhiyun }; 119*4882a593Smuzhiyun 120*4882a593Smuzhiyun struct idmac_video_param { 121*4882a593Smuzhiyun unsigned short in_width; 122*4882a593Smuzhiyun unsigned short in_height; 123*4882a593Smuzhiyun uint32_t in_pixel_fmt; 124*4882a593Smuzhiyun unsigned short out_width; 125*4882a593Smuzhiyun unsigned short out_height; 126*4882a593Smuzhiyun uint32_t out_pixel_fmt; 127*4882a593Smuzhiyun unsigned short out_stride; 128*4882a593Smuzhiyun bool graphics_combine_en; 129*4882a593Smuzhiyun bool global_alpha_en; 130*4882a593Smuzhiyun bool key_color_en; 131*4882a593Smuzhiyun enum display_port disp; 132*4882a593Smuzhiyun unsigned short out_left; 133*4882a593Smuzhiyun unsigned short out_top; 134*4882a593Smuzhiyun }; 135*4882a593Smuzhiyun 136*4882a593Smuzhiyun /* 137*4882a593Smuzhiyun * Union of initialization parameters for a logical channel. So far only video 138*4882a593Smuzhiyun * parameters are used. 139*4882a593Smuzhiyun */ 140*4882a593Smuzhiyun union ipu_channel_param { 141*4882a593Smuzhiyun struct idmac_video_param video; 142*4882a593Smuzhiyun }; 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun struct idmac_tx_desc { 145*4882a593Smuzhiyun struct dma_async_tx_descriptor txd; 146*4882a593Smuzhiyun struct scatterlist *sg; /* scatterlist for this */ 147*4882a593Smuzhiyun unsigned int sg_len; /* tx-descriptor. */ 148*4882a593Smuzhiyun struct list_head list; 149*4882a593Smuzhiyun }; 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun struct idmac_channel { 152*4882a593Smuzhiyun struct dma_chan dma_chan; 153*4882a593Smuzhiyun dma_cookie_t completed; /* last completed cookie */ 154*4882a593Smuzhiyun union ipu_channel_param params; 155*4882a593Smuzhiyun enum ipu_channel link; /* input channel, linked to the output */ 156*4882a593Smuzhiyun enum ipu_channel_status status; 157*4882a593Smuzhiyun void *client; /* Only one client per channel */ 158*4882a593Smuzhiyun unsigned int n_tx_desc; 159*4882a593Smuzhiyun struct idmac_tx_desc *desc; /* allocated tx-descriptors */ 160*4882a593Smuzhiyun struct scatterlist *sg[2]; /* scatterlist elements in buffer-0 and -1 */ 161*4882a593Smuzhiyun struct list_head free_list; /* free tx-descriptors */ 162*4882a593Smuzhiyun struct list_head queue; /* queued tx-descriptors */ 163*4882a593Smuzhiyun spinlock_t lock; /* protects sg[0,1], queue */ 164*4882a593Smuzhiyun struct mutex chan_mutex; /* protects status, cookie, free_list */ 165*4882a593Smuzhiyun bool sec_chan_en; 166*4882a593Smuzhiyun int active_buffer; 167*4882a593Smuzhiyun unsigned int eof_irq; 168*4882a593Smuzhiyun char eof_name[16]; /* EOF IRQ name for request_irq() */ 169*4882a593Smuzhiyun }; 170*4882a593Smuzhiyun 171*4882a593Smuzhiyun #define to_tx_desc(tx) container_of(tx, struct idmac_tx_desc, txd) 172*4882a593Smuzhiyun #define to_idmac_chan(c) container_of(c, struct idmac_channel, dma_chan) 173*4882a593Smuzhiyun 174*4882a593Smuzhiyun #endif /* __LINUX_DMA_IPU_DMA_H */ 175