1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Driver for the High Speed UART DMA
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright (C) 2015 Intel Corporation
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #ifndef _DMA_HSU_H
9*4882a593Smuzhiyun #define _DMA_HSU_H
10*4882a593Smuzhiyun
11*4882a593Smuzhiyun #include <linux/device.h>
12*4882a593Smuzhiyun #include <linux/interrupt.h>
13*4882a593Smuzhiyun
14*4882a593Smuzhiyun #include <linux/platform_data/dma-hsu.h>
15*4882a593Smuzhiyun
16*4882a593Smuzhiyun struct hsu_dma;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /**
19*4882a593Smuzhiyun * struct hsu_dma_chip - representation of HSU DMA hardware
20*4882a593Smuzhiyun * @dev: struct device of the DMA controller
21*4882a593Smuzhiyun * @irq: irq line
22*4882a593Smuzhiyun * @regs: memory mapped I/O space
23*4882a593Smuzhiyun * @length: I/O space length
24*4882a593Smuzhiyun * @offset: offset of the I/O space where registers are located
25*4882a593Smuzhiyun * @hsu: struct hsu_dma that is filed by ->probe()
26*4882a593Smuzhiyun * @pdata: platform data for the DMA controller if provided
27*4882a593Smuzhiyun */
28*4882a593Smuzhiyun struct hsu_dma_chip {
29*4882a593Smuzhiyun struct device *dev;
30*4882a593Smuzhiyun int irq;
31*4882a593Smuzhiyun void __iomem *regs;
32*4882a593Smuzhiyun unsigned int length;
33*4882a593Smuzhiyun unsigned int offset;
34*4882a593Smuzhiyun struct hsu_dma *hsu;
35*4882a593Smuzhiyun };
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_HSU_DMA)
38*4882a593Smuzhiyun /* Export to the internal users */
39*4882a593Smuzhiyun int hsu_dma_get_status(struct hsu_dma_chip *chip, unsigned short nr,
40*4882a593Smuzhiyun u32 *status);
41*4882a593Smuzhiyun int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr, u32 status);
42*4882a593Smuzhiyun
43*4882a593Smuzhiyun /* Export to the platform drivers */
44*4882a593Smuzhiyun int hsu_dma_probe(struct hsu_dma_chip *chip);
45*4882a593Smuzhiyun int hsu_dma_remove(struct hsu_dma_chip *chip);
46*4882a593Smuzhiyun #else
hsu_dma_get_status(struct hsu_dma_chip * chip,unsigned short nr,u32 * status)47*4882a593Smuzhiyun static inline int hsu_dma_get_status(struct hsu_dma_chip *chip,
48*4882a593Smuzhiyun unsigned short nr, u32 *status)
49*4882a593Smuzhiyun {
50*4882a593Smuzhiyun return 0;
51*4882a593Smuzhiyun }
hsu_dma_do_irq(struct hsu_dma_chip * chip,unsigned short nr,u32 status)52*4882a593Smuzhiyun static inline int hsu_dma_do_irq(struct hsu_dma_chip *chip, unsigned short nr,
53*4882a593Smuzhiyun u32 status)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun return 0;
56*4882a593Smuzhiyun }
hsu_dma_probe(struct hsu_dma_chip * chip)57*4882a593Smuzhiyun static inline int hsu_dma_probe(struct hsu_dma_chip *chip) { return -ENODEV; }
hsu_dma_remove(struct hsu_dma_chip * chip)58*4882a593Smuzhiyun static inline int hsu_dma_remove(struct hsu_dma_chip *chip) { return 0; }
59*4882a593Smuzhiyun #endif /* CONFIG_HSU_DMA */
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #endif /* _DMA_HSU_H */
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