1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2013 Xilinx Inc. 4*4882a593Smuzhiyun * Copyright (C) 2012 National Instruments 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef __LINUX_CLK_ZYNQ_H_ 8*4882a593Smuzhiyun #define __LINUX_CLK_ZYNQ_H_ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #include <linux/spinlock.h> 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun void zynq_clock_init(void); 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct clk *clk_register_zynq_pll(const char *name, const char *parent, 15*4882a593Smuzhiyun void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, 16*4882a593Smuzhiyun spinlock_t *lock); 17*4882a593Smuzhiyun #endif 18