1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * include/linux/clk/at91_pmc.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2005 Ivan Kokshaysky 6*4882a593Smuzhiyun * Copyright (C) SAN People 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * Power Management Controller (PMC) - System peripherals registers. 9*4882a593Smuzhiyun * Based on AT91RM9200 datasheet revision E. 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef AT91_PMC_H 13*4882a593Smuzhiyun #define AT91_PMC_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun #define AT91_PMC_V1 (1) /* PMC version 1 */ 16*4882a593Smuzhiyun #define AT91_PMC_V2 (2) /* PMC version 2 [SAM9X60] */ 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define AT91_PMC_SCER 0x00 /* System Clock Enable Register */ 19*4882a593Smuzhiyun #define AT91_PMC_SCDR 0x04 /* System Clock Disable Register */ 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define AT91_PMC_SCSR 0x08 /* System Clock Status Register */ 22*4882a593Smuzhiyun #define AT91_PMC_PCK (1 << 0) /* Processor Clock */ 23*4882a593Smuzhiyun #define AT91RM9200_PMC_UDP (1 << 1) /* USB Devcice Port Clock [AT91RM9200 only] */ 24*4882a593Smuzhiyun #define AT91RM9200_PMC_MCKUDP (1 << 2) /* USB Device Port Master Clock Automatic Disable on Suspend [AT91RM9200 only] */ 25*4882a593Smuzhiyun #define AT91RM9200_PMC_UHP (1 << 4) /* USB Host Port Clock [AT91RM9200 only] */ 26*4882a593Smuzhiyun #define AT91SAM926x_PMC_UHP (1 << 6) /* USB Host Port Clock [AT91SAM926x only] */ 27*4882a593Smuzhiyun #define AT91SAM926x_PMC_UDP (1 << 7) /* USB Devcice Port Clock [AT91SAM926x only] */ 28*4882a593Smuzhiyun #define AT91_PMC_PCK0 (1 << 8) /* Programmable Clock 0 */ 29*4882a593Smuzhiyun #define AT91_PMC_PCK1 (1 << 9) /* Programmable Clock 1 */ 30*4882a593Smuzhiyun #define AT91_PMC_PCK2 (1 << 10) /* Programmable Clock 2 */ 31*4882a593Smuzhiyun #define AT91_PMC_PCK3 (1 << 11) /* Programmable Clock 3 */ 32*4882a593Smuzhiyun #define AT91_PMC_PCK4 (1 << 12) /* Programmable Clock 4 [AT572D940HF only] */ 33*4882a593Smuzhiyun #define AT91_PMC_HCK0 (1 << 16) /* AHB Clock (USB host) [AT91SAM9261 only] */ 34*4882a593Smuzhiyun #define AT91_PMC_HCK1 (1 << 17) /* AHB Clock (LCD) [AT91SAM9261 only] */ 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #define AT91_PMC_PLL_CTRL0 0x0C /* PLL Control Register 0 [for SAM9X60] */ 37*4882a593Smuzhiyun #define AT91_PMC_PLL_CTRL0_ENPLL (1 << 28) /* Enable PLL */ 38*4882a593Smuzhiyun #define AT91_PMC_PLL_CTRL0_ENPLLCK (1 << 29) /* Enable PLL clock for PMC */ 39*4882a593Smuzhiyun #define AT91_PMC_PLL_CTRL0_ENLOCK (1 << 31) /* Enable PLL lock */ 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun #define AT91_PMC_PLL_CTRL1 0x10 /* PLL Control Register 1 [for SAM9X60] */ 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define AT91_PMC_PCER 0x10 /* Peripheral Clock Enable Register */ 44*4882a593Smuzhiyun #define AT91_PMC_PCDR 0x14 /* Peripheral Clock Disable Register */ 45*4882a593Smuzhiyun #define AT91_PMC_PCSR 0x18 /* Peripheral Clock Status Register */ 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define AT91_PMC_PLL_ACR 0x18 /* PLL Analog Control Register [for SAM9X60] */ 48*4882a593Smuzhiyun #define AT91_PMC_PLL_ACR_DEFAULT_UPLL 0x12020010UL /* Default PLL ACR value for UPLL */ 49*4882a593Smuzhiyun #define AT91_PMC_PLL_ACR_DEFAULT_PLLA 0x00020010UL /* Default PLL ACR value for PLLA */ 50*4882a593Smuzhiyun #define AT91_PMC_PLL_ACR_UTMIVR (1 << 12) /* UPLL Voltage regulator Control */ 51*4882a593Smuzhiyun #define AT91_PMC_PLL_ACR_UTMIBG (1 << 13) /* UPLL Bandgap Control */ 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define AT91_CKGR_UCKR 0x1C /* UTMI Clock Register [some SAM9] */ 54*4882a593Smuzhiyun #define AT91_PMC_UPLLEN (1 << 16) /* UTMI PLL Enable */ 55*4882a593Smuzhiyun #define AT91_PMC_UPLLCOUNT (0xf << 20) /* UTMI PLL Start-up Time */ 56*4882a593Smuzhiyun #define AT91_PMC_BIASEN (1 << 24) /* UTMI BIAS Enable */ 57*4882a593Smuzhiyun #define AT91_PMC_BIASCOUNT (0xf << 28) /* UTMI BIAS Start-up Time */ 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun #define AT91_PMC_PLL_UPDT 0x1C /* PMC PLL update register [for SAM9X60] */ 60*4882a593Smuzhiyun #define AT91_PMC_PLL_UPDT_UPDATE (1 << 8) /* Update PLL settings */ 61*4882a593Smuzhiyun #define AT91_PMC_PLL_UPDT_ID (1 << 0) /* PLL ID */ 62*4882a593Smuzhiyun #define AT91_PMC_PLL_UPDT_ID_MSK (0xf) /* PLL ID mask */ 63*4882a593Smuzhiyun #define AT91_PMC_PLL_UPDT_STUPTIM (0xff << 16) /* Startup time */ 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun #define AT91_CKGR_MOR 0x20 /* Main Oscillator Register [not on SAM9RL] */ 66*4882a593Smuzhiyun #define AT91_PMC_MOSCEN (1 << 0) /* Main Oscillator Enable */ 67*4882a593Smuzhiyun #define AT91_PMC_OSCBYPASS (1 << 1) /* Oscillator Bypass */ 68*4882a593Smuzhiyun #define AT91_PMC_WAITMODE (1 << 2) /* Wait Mode Command */ 69*4882a593Smuzhiyun #define AT91_PMC_MOSCRCEN (1 << 3) /* Main On-Chip RC Oscillator Enable [some SAM9] */ 70*4882a593Smuzhiyun #define AT91_PMC_OSCOUNT (0xff << 8) /* Main Oscillator Start-up Time */ 71*4882a593Smuzhiyun #define AT91_PMC_KEY_MASK (0xff << 16) 72*4882a593Smuzhiyun #define AT91_PMC_KEY (0x37 << 16) /* MOR Writing Key */ 73*4882a593Smuzhiyun #define AT91_PMC_MOSCSEL (1 << 24) /* Main Oscillator Selection [some SAM9] */ 74*4882a593Smuzhiyun #define AT91_PMC_CFDEN (1 << 25) /* Clock Failure Detector Enable [some SAM9] */ 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun #define AT91_CKGR_MCFR 0x24 /* Main Clock Frequency Register */ 77*4882a593Smuzhiyun #define AT91_PMC_MAINF (0xffff << 0) /* Main Clock Frequency */ 78*4882a593Smuzhiyun #define AT91_PMC_MAINRDY (1 << 16) /* Main Clock Ready */ 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun #define AT91_CKGR_PLLAR 0x28 /* PLL A Register */ 81*4882a593Smuzhiyun #define AT91_CKGR_PLLBR 0x2c /* PLL B Register */ 82*4882a593Smuzhiyun #define AT91_PMC_DIV (0xff << 0) /* Divider */ 83*4882a593Smuzhiyun #define AT91_PMC_PLLCOUNT (0x3f << 8) /* PLL Counter */ 84*4882a593Smuzhiyun #define AT91_PMC_OUT (3 << 14) /* PLL Clock Frequency Range */ 85*4882a593Smuzhiyun #define AT91_PMC_MUL (0x7ff << 16) /* PLL Multiplier */ 86*4882a593Smuzhiyun #define AT91_PMC_MUL_GET(n) ((n) >> 16 & 0x7ff) 87*4882a593Smuzhiyun #define AT91_PMC3_MUL (0x7f << 18) /* PLL Multiplier [SAMA5 only] */ 88*4882a593Smuzhiyun #define AT91_PMC3_MUL_GET(n) ((n) >> 18 & 0x7f) 89*4882a593Smuzhiyun #define AT91_PMC_USBDIV (3 << 28) /* USB Divisor (PLLB only) */ 90*4882a593Smuzhiyun #define AT91_PMC_USBDIV_1 (0 << 28) 91*4882a593Smuzhiyun #define AT91_PMC_USBDIV_2 (1 << 28) 92*4882a593Smuzhiyun #define AT91_PMC_USBDIV_4 (2 << 28) 93*4882a593Smuzhiyun #define AT91_PMC_USB96M (1 << 28) /* Divider by 2 Enable (PLLB only) */ 94*4882a593Smuzhiyun 95*4882a593Smuzhiyun #define AT91_PMC_CPU_CKR 0x28 /* CPU Clock Register */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define AT91_PMC_MCKR 0x30 /* Master Clock Register */ 98*4882a593Smuzhiyun #define AT91_PMC_CSS (3 << 0) /* Master Clock Selection */ 99*4882a593Smuzhiyun #define AT91_PMC_CSS_SLOW (0 << 0) 100*4882a593Smuzhiyun #define AT91_PMC_CSS_MAIN (1 << 0) 101*4882a593Smuzhiyun #define AT91_PMC_CSS_PLLA (2 << 0) 102*4882a593Smuzhiyun #define AT91_PMC_CSS_PLLB (3 << 0) 103*4882a593Smuzhiyun #define AT91_PMC_CSS_UPLL (3 << 0) /* [some SAM9 only] */ 104*4882a593Smuzhiyun #define PMC_PRES_OFFSET 2 105*4882a593Smuzhiyun #define AT91_PMC_PRES (7 << PMC_PRES_OFFSET) /* Master Clock Prescaler */ 106*4882a593Smuzhiyun #define AT91_PMC_PRES_1 (0 << PMC_PRES_OFFSET) 107*4882a593Smuzhiyun #define AT91_PMC_PRES_2 (1 << PMC_PRES_OFFSET) 108*4882a593Smuzhiyun #define AT91_PMC_PRES_4 (2 << PMC_PRES_OFFSET) 109*4882a593Smuzhiyun #define AT91_PMC_PRES_8 (3 << PMC_PRES_OFFSET) 110*4882a593Smuzhiyun #define AT91_PMC_PRES_16 (4 << PMC_PRES_OFFSET) 111*4882a593Smuzhiyun #define AT91_PMC_PRES_32 (5 << PMC_PRES_OFFSET) 112*4882a593Smuzhiyun #define AT91_PMC_PRES_64 (6 << PMC_PRES_OFFSET) 113*4882a593Smuzhiyun #define PMC_ALT_PRES_OFFSET 4 114*4882a593Smuzhiyun #define AT91_PMC_ALT_PRES (7 << PMC_ALT_PRES_OFFSET) /* Master Clock Prescaler [alternate location] */ 115*4882a593Smuzhiyun #define AT91_PMC_ALT_PRES_1 (0 << PMC_ALT_PRES_OFFSET) 116*4882a593Smuzhiyun #define AT91_PMC_ALT_PRES_2 (1 << PMC_ALT_PRES_OFFSET) 117*4882a593Smuzhiyun #define AT91_PMC_ALT_PRES_4 (2 << PMC_ALT_PRES_OFFSET) 118*4882a593Smuzhiyun #define AT91_PMC_ALT_PRES_8 (3 << PMC_ALT_PRES_OFFSET) 119*4882a593Smuzhiyun #define AT91_PMC_ALT_PRES_16 (4 << PMC_ALT_PRES_OFFSET) 120*4882a593Smuzhiyun #define AT91_PMC_ALT_PRES_32 (5 << PMC_ALT_PRES_OFFSET) 121*4882a593Smuzhiyun #define AT91_PMC_ALT_PRES_64 (6 << PMC_ALT_PRES_OFFSET) 122*4882a593Smuzhiyun #define AT91_PMC_MDIV (3 << 8) /* Master Clock Division */ 123*4882a593Smuzhiyun #define AT91RM9200_PMC_MDIV_1 (0 << 8) /* [AT91RM9200 only] */ 124*4882a593Smuzhiyun #define AT91RM9200_PMC_MDIV_2 (1 << 8) 125*4882a593Smuzhiyun #define AT91RM9200_PMC_MDIV_3 (2 << 8) 126*4882a593Smuzhiyun #define AT91RM9200_PMC_MDIV_4 (3 << 8) 127*4882a593Smuzhiyun #define AT91SAM9_PMC_MDIV_1 (0 << 8) /* [SAM9 only] */ 128*4882a593Smuzhiyun #define AT91SAM9_PMC_MDIV_2 (1 << 8) 129*4882a593Smuzhiyun #define AT91SAM9_PMC_MDIV_4 (2 << 8) 130*4882a593Smuzhiyun #define AT91SAM9_PMC_MDIV_6 (3 << 8) /* [some SAM9 only] */ 131*4882a593Smuzhiyun #define AT91SAM9_PMC_MDIV_3 (3 << 8) /* [some SAM9 only] */ 132*4882a593Smuzhiyun #define AT91_PMC_PDIV (1 << 12) /* Processor Clock Division [some SAM9 only] */ 133*4882a593Smuzhiyun #define AT91_PMC_PDIV_1 (0 << 12) 134*4882a593Smuzhiyun #define AT91_PMC_PDIV_2 (1 << 12) 135*4882a593Smuzhiyun #define AT91_PMC_PLLADIV2 (1 << 12) /* PLLA divisor by 2 [some SAM9 only] */ 136*4882a593Smuzhiyun #define AT91_PMC_PLLADIV2_OFF (0 << 12) 137*4882a593Smuzhiyun #define AT91_PMC_PLLADIV2_ON (1 << 12) 138*4882a593Smuzhiyun #define AT91_PMC_H32MXDIV BIT(24) 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun #define AT91_PMC_XTALF 0x34 /* Main XTAL Frequency Register [SAMA7G5 only] */ 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #define AT91_PMC_USB 0x38 /* USB Clock Register [some SAM9 only] */ 143*4882a593Smuzhiyun #define AT91_PMC_USBS (0x1 << 0) /* USB OHCI Input clock selection */ 144*4882a593Smuzhiyun #define AT91_PMC_USBS_PLLA (0 << 0) 145*4882a593Smuzhiyun #define AT91_PMC_USBS_UPLL (1 << 0) 146*4882a593Smuzhiyun #define AT91_PMC_USBS_PLLB (1 << 0) /* [AT91SAMN12 only] */ 147*4882a593Smuzhiyun #define AT91_PMC_OHCIUSBDIV (0xF << 8) /* Divider for USB OHCI Clock */ 148*4882a593Smuzhiyun #define AT91_PMC_OHCIUSBDIV_1 (0x0 << 8) 149*4882a593Smuzhiyun #define AT91_PMC_OHCIUSBDIV_2 (0x1 << 8) 150*4882a593Smuzhiyun 151*4882a593Smuzhiyun #define AT91_PMC_SMD 0x3c /* Soft Modem Clock Register [some SAM9 only] */ 152*4882a593Smuzhiyun #define AT91_PMC_SMDS (0x1 << 0) /* SMD input clock selection */ 153*4882a593Smuzhiyun #define AT91_PMC_SMD_DIV (0x1f << 8) /* SMD input clock divider */ 154*4882a593Smuzhiyun #define AT91_PMC_SMDDIV(n) (((n) << 8) & AT91_PMC_SMD_DIV) 155*4882a593Smuzhiyun 156*4882a593Smuzhiyun #define AT91_PMC_PCKR(n) (0x40 + ((n) * 4)) /* Programmable Clock 0-N Registers */ 157*4882a593Smuzhiyun #define AT91_PMC_ALT_PCKR_CSS (0x7 << 0) /* Programmable Clock Source Selection [alternate length] */ 158*4882a593Smuzhiyun #define AT91_PMC_CSS_MASTER (4 << 0) /* [some SAM9 only] */ 159*4882a593Smuzhiyun #define AT91_PMC_CSSMCK (0x1 << 8) /* CSS or Master Clock Selection */ 160*4882a593Smuzhiyun #define AT91_PMC_CSSMCK_CSS (0 << 8) 161*4882a593Smuzhiyun #define AT91_PMC_CSSMCK_MCK (1 << 8) 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun #define AT91_PMC_IER 0x60 /* Interrupt Enable Register */ 164*4882a593Smuzhiyun #define AT91_PMC_IDR 0x64 /* Interrupt Disable Register */ 165*4882a593Smuzhiyun #define AT91_PMC_SR 0x68 /* Status Register */ 166*4882a593Smuzhiyun #define AT91_PMC_MOSCS (1 << 0) /* MOSCS Flag */ 167*4882a593Smuzhiyun #define AT91_PMC_LOCKA (1 << 1) /* PLLA Lock */ 168*4882a593Smuzhiyun #define AT91_PMC_LOCKB (1 << 2) /* PLLB Lock */ 169*4882a593Smuzhiyun #define AT91_PMC_MCKRDY (1 << 3) /* Master Clock */ 170*4882a593Smuzhiyun #define AT91_PMC_LOCKU (1 << 6) /* UPLL Lock [some SAM9] */ 171*4882a593Smuzhiyun #define AT91_PMC_OSCSEL (1 << 7) /* Slow Oscillator Selection [some SAM9] */ 172*4882a593Smuzhiyun #define AT91_PMC_PCK0RDY (1 << 8) /* Programmable Clock 0 */ 173*4882a593Smuzhiyun #define AT91_PMC_PCK1RDY (1 << 9) /* Programmable Clock 1 */ 174*4882a593Smuzhiyun #define AT91_PMC_PCK2RDY (1 << 10) /* Programmable Clock 2 */ 175*4882a593Smuzhiyun #define AT91_PMC_PCK3RDY (1 << 11) /* Programmable Clock 3 */ 176*4882a593Smuzhiyun #define AT91_PMC_MOSCSELS (1 << 16) /* Main Oscillator Selection [some SAM9] */ 177*4882a593Smuzhiyun #define AT91_PMC_MOSCRCS (1 << 17) /* Main On-Chip RC [some SAM9] */ 178*4882a593Smuzhiyun #define AT91_PMC_CFDEV (1 << 18) /* Clock Failure Detector Event [some SAM9] */ 179*4882a593Smuzhiyun #define AT91_PMC_GCKRDY (1 << 24) /* Generated Clocks */ 180*4882a593Smuzhiyun #define AT91_PMC_MCKXRDY (1 << 26) /* Master Clock x [x=1..4] Ready Status */ 181*4882a593Smuzhiyun #define AT91_PMC_IMR 0x6c /* Interrupt Mask Register */ 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun #define AT91_PMC_FSMR 0x70 /* Fast Startup Mode Register */ 184*4882a593Smuzhiyun #define AT91_PMC_FSTT(n) BIT(n) 185*4882a593Smuzhiyun #define AT91_PMC_RTTAL BIT(16) 186*4882a593Smuzhiyun #define AT91_PMC_RTCAL BIT(17) /* RTC Alarm Enable */ 187*4882a593Smuzhiyun #define AT91_PMC_USBAL BIT(18) /* USB Resume Enable */ 188*4882a593Smuzhiyun #define AT91_PMC_SDMMC_CD BIT(19) /* SDMMC Card Detect Enable */ 189*4882a593Smuzhiyun #define AT91_PMC_LPM BIT(20) /* Low-power Mode */ 190*4882a593Smuzhiyun #define AT91_PMC_RXLP_MCE BIT(24) /* Backup UART Receive Enable */ 191*4882a593Smuzhiyun #define AT91_PMC_ACC_CE BIT(25) /* ACC Enable */ 192*4882a593Smuzhiyun 193*4882a593Smuzhiyun #define AT91_PMC_FSPR 0x74 /* Fast Startup Polarity Reg */ 194*4882a593Smuzhiyun 195*4882a593Smuzhiyun #define AT91_PMC_FS_INPUT_MASK 0x7ff 196*4882a593Smuzhiyun 197*4882a593Smuzhiyun #define AT91_PMC_PLLICPR 0x80 /* PLL Charge Pump Current Register */ 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun #define AT91_PMC_PROT 0xe4 /* Write Protect Mode Register [some SAM9] */ 200*4882a593Smuzhiyun #define AT91_PMC_WPEN (0x1 << 0) /* Write Protect Enable */ 201*4882a593Smuzhiyun #define AT91_PMC_WPKEY (0xffffff << 8) /* Write Protect Key */ 202*4882a593Smuzhiyun #define AT91_PMC_PROTKEY (0x504d43 << 8) /* Activation Code */ 203*4882a593Smuzhiyun 204*4882a593Smuzhiyun #define AT91_PMC_WPSR 0xe8 /* Write Protect Status Register [some SAM9] */ 205*4882a593Smuzhiyun #define AT91_PMC_WPVS (0x1 << 0) /* Write Protect Violation Status */ 206*4882a593Smuzhiyun #define AT91_PMC_WPVSRC (0xffff << 8) /* Write Protect Violation Source */ 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define AT91_PMC_PLL_ISR0 0xEC /* PLL Interrupt Status Register 0 [SAM9X60 only] */ 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun #define AT91_PMC_PCER1 0x100 /* Peripheral Clock Enable Register 1 [SAMA5 only]*/ 211*4882a593Smuzhiyun #define AT91_PMC_PCDR1 0x104 /* Peripheral Clock Enable Register 1 */ 212*4882a593Smuzhiyun #define AT91_PMC_PCSR1 0x108 /* Peripheral Clock Enable Register 1 */ 213*4882a593Smuzhiyun 214*4882a593Smuzhiyun #define AT91_PMC_PCR 0x10c /* Peripheral Control Register [some SAM9 and SAMA5] */ 215*4882a593Smuzhiyun #define AT91_PMC_PCR_PID_MASK 0x3f 216*4882a593Smuzhiyun #define AT91_PMC_PCR_CMD (0x1 << 12) /* Command (read=0, write=1) */ 217*4882a593Smuzhiyun #define AT91_PMC_PCR_GCKDIV_MASK GENMASK(27, 20) 218*4882a593Smuzhiyun #define AT91_PMC_PCR_EN (0x1 << 28) /* Enable */ 219*4882a593Smuzhiyun #define AT91_PMC_PCR_GCKEN (0x1 << 29) /* GCK Enable */ 220*4882a593Smuzhiyun 221*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL0 0x14c 222*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_PLLEN (1 << 0) 223*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_PADEN (1 << 1) 224*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_PMCEN (1 << 2) 225*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_RESETN (1 << 3) 226*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_ND_OFFSET 8 227*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_ND_MASK (0x7f << AT91_PMC_AUDIO_PLL_ND_OFFSET) 228*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_ND(n) ((n) << AT91_PMC_AUDIO_PLL_ND_OFFSET) 229*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPMC_OFFSET 16 230*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPMC_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) 231*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPMC(n) ((n) << AT91_PMC_AUDIO_PLL_QDPMC_OFFSET) 232*4882a593Smuzhiyun 233*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL1 0x150 234*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_FRACR_MASK 0x3fffff 235*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 24 236*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD_MASK (0x7f << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) 237*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_OFFSET) 238*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET AT91_PMC_AUDIO_PLL_QDPAD_OFFSET 239*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD_DIV_MASK (0x3 << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) 240*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD_DIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_DIV_OFFSET) 241*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET 26 242*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX 0x1f 243*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MASK (AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_MAX << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) 244*4882a593Smuzhiyun #define AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV(n) ((n) << AT91_PMC_AUDIO_PLL_QDPAD_EXTDIV_OFFSET) 245*4882a593Smuzhiyun 246*4882a593Smuzhiyun #endif 247