1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _CAN_PLATFORM_SJA1000_H 3*4882a593Smuzhiyun #define _CAN_PLATFORM_SJA1000_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* clock divider register */ 6*4882a593Smuzhiyun #define CDR_CLKOUT_MASK 0x07 7*4882a593Smuzhiyun #define CDR_CLK_OFF 0x08 /* Clock off (CLKOUT pin) */ 8*4882a593Smuzhiyun #define CDR_RXINPEN 0x20 /* TX1 output is RX irq output */ 9*4882a593Smuzhiyun #define CDR_CBP 0x40 /* CAN input comparator bypass */ 10*4882a593Smuzhiyun #define CDR_PELICAN 0x80 /* PeliCAN mode */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* output control register */ 13*4882a593Smuzhiyun #define OCR_MODE_BIPHASE 0x00 14*4882a593Smuzhiyun #define OCR_MODE_TEST 0x01 15*4882a593Smuzhiyun #define OCR_MODE_NORMAL 0x02 16*4882a593Smuzhiyun #define OCR_MODE_CLOCK 0x03 17*4882a593Smuzhiyun #define OCR_MODE_MASK 0x03 18*4882a593Smuzhiyun #define OCR_TX0_INVERT 0x04 19*4882a593Smuzhiyun #define OCR_TX0_PULLDOWN 0x08 20*4882a593Smuzhiyun #define OCR_TX0_PULLUP 0x10 21*4882a593Smuzhiyun #define OCR_TX0_PUSHPULL 0x18 22*4882a593Smuzhiyun #define OCR_TX1_INVERT 0x20 23*4882a593Smuzhiyun #define OCR_TX1_PULLDOWN 0x40 24*4882a593Smuzhiyun #define OCR_TX1_PULLUP 0x80 25*4882a593Smuzhiyun #define OCR_TX1_PUSHPULL 0xc0 26*4882a593Smuzhiyun #define OCR_TX_MASK 0xfc 27*4882a593Smuzhiyun #define OCR_TX_SHIFT 2 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun struct sja1000_platform_data { 30*4882a593Smuzhiyun u32 osc_freq; /* CAN bus oscillator frequency in Hz */ 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun u8 ocr; /* output control register */ 33*4882a593Smuzhiyun u8 cdr; /* clock divider register */ 34*4882a593Smuzhiyun }; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun #endif /* !_CAN_PLATFORM_SJA1000_H */ 37