1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _CAN_PLATFORM_CC770_H 3*4882a593Smuzhiyun #define _CAN_PLATFORM_CC770_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun /* CPU Interface Register (0x02) */ 6*4882a593Smuzhiyun #define CPUIF_CEN 0x01 /* Clock Out Enable */ 7*4882a593Smuzhiyun #define CPUIF_MUX 0x04 /* Multiplex */ 8*4882a593Smuzhiyun #define CPUIF_SLP 0x08 /* Sleep */ 9*4882a593Smuzhiyun #define CPUIF_PWD 0x10 /* Power Down Mode */ 10*4882a593Smuzhiyun #define CPUIF_DMC 0x20 /* Divide Memory Clock */ 11*4882a593Smuzhiyun #define CPUIF_DSC 0x40 /* Divide System Clock */ 12*4882a593Smuzhiyun #define CPUIF_RST 0x80 /* Hardware Reset Status */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Clock Out Register (0x1f) */ 15*4882a593Smuzhiyun #define CLKOUT_CD_MASK 0x0f /* Clock Divider mask */ 16*4882a593Smuzhiyun #define CLKOUT_SL_MASK 0x30 /* Slew Rate mask */ 17*4882a593Smuzhiyun #define CLKOUT_SL_SHIFT 4 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Bus Configuration Register (0x2f) */ 20*4882a593Smuzhiyun #define BUSCFG_DR0 0x01 /* Disconnect RX0 Input / Select RX input */ 21*4882a593Smuzhiyun #define BUSCFG_DR1 0x02 /* Disconnect RX1 Input / Silent mode */ 22*4882a593Smuzhiyun #define BUSCFG_DT1 0x08 /* Disconnect TX1 Output */ 23*4882a593Smuzhiyun #define BUSCFG_POL 0x20 /* Polarity dominant or recessive */ 24*4882a593Smuzhiyun #define BUSCFG_CBY 0x40 /* Input Comparator Bypass */ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun struct cc770_platform_data { 27*4882a593Smuzhiyun u32 osc_freq; /* CAN bus oscillator frequency in Hz */ 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun u8 cir; /* CPU Interface Register */ 30*4882a593Smuzhiyun u8 cor; /* Clock Out Register */ 31*4882a593Smuzhiyun u8 bcr; /* Bus Configuration Register */ 32*4882a593Smuzhiyun }; 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #endif /* !_CAN_PLATFORM_CC770_H */ 35