1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun #ifndef _LINUX_BRCMPHY_H 3*4882a593Smuzhiyun #define _LINUX_BRCMPHY_H 4*4882a593Smuzhiyun 5*4882a593Smuzhiyun #include <linux/phy.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun /* All Broadcom Ethernet switches have a pseudo-PHY at address 30 which is used 8*4882a593Smuzhiyun * to configure the switch internal registers via MDIO accesses. 9*4882a593Smuzhiyun */ 10*4882a593Smuzhiyun #define BRCM_PSEUDO_PHY_ADDR 30 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define PHY_ID_BCM50610 0x0143bd60 13*4882a593Smuzhiyun #define PHY_ID_BCM50610M 0x0143bd70 14*4882a593Smuzhiyun #define PHY_ID_BCM5241 0x0143bc30 15*4882a593Smuzhiyun #define PHY_ID_BCMAC131 0x0143bc70 16*4882a593Smuzhiyun #define PHY_ID_BCM5481 0x0143bca0 17*4882a593Smuzhiyun #define PHY_ID_BCM5395 0x0143bcf0 18*4882a593Smuzhiyun #define PHY_ID_BCM53125 0x03625f20 19*4882a593Smuzhiyun #define PHY_ID_BCM54810 0x03625d00 20*4882a593Smuzhiyun #define PHY_ID_BCM54811 0x03625cc0 21*4882a593Smuzhiyun #define PHY_ID_BCM5482 0x0143bcb0 22*4882a593Smuzhiyun #define PHY_ID_BCM5411 0x00206070 23*4882a593Smuzhiyun #define PHY_ID_BCM5421 0x002060e0 24*4882a593Smuzhiyun #define PHY_ID_BCM54210E 0x600d84a0 25*4882a593Smuzhiyun #define PHY_ID_BCM5464 0x002060b0 26*4882a593Smuzhiyun #define PHY_ID_BCM5461 0x002060c0 27*4882a593Smuzhiyun #define PHY_ID_BCM54612E 0x03625e60 28*4882a593Smuzhiyun #define PHY_ID_BCM54616S 0x03625d10 29*4882a593Smuzhiyun #define PHY_ID_BCM54140 0xae025009 30*4882a593Smuzhiyun #define PHY_ID_BCM57780 0x03625d90 31*4882a593Smuzhiyun #define PHY_ID_BCM89610 0x03625cd0 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define PHY_ID_BCM72113 0x35905310 34*4882a593Smuzhiyun #define PHY_ID_BCM7250 0xae025280 35*4882a593Smuzhiyun #define PHY_ID_BCM7255 0xae025120 36*4882a593Smuzhiyun #define PHY_ID_BCM7260 0xae025190 37*4882a593Smuzhiyun #define PHY_ID_BCM7268 0xae025090 38*4882a593Smuzhiyun #define PHY_ID_BCM7271 0xae0253b0 39*4882a593Smuzhiyun #define PHY_ID_BCM7278 0xae0251a0 40*4882a593Smuzhiyun #define PHY_ID_BCM7364 0xae025260 41*4882a593Smuzhiyun #define PHY_ID_BCM7366 0x600d8490 42*4882a593Smuzhiyun #define PHY_ID_BCM7346 0x600d8650 43*4882a593Smuzhiyun #define PHY_ID_BCM7362 0x600d84b0 44*4882a593Smuzhiyun #define PHY_ID_BCM7425 0x600d86b0 45*4882a593Smuzhiyun #define PHY_ID_BCM7429 0x600d8730 46*4882a593Smuzhiyun #define PHY_ID_BCM7435 0x600d8750 47*4882a593Smuzhiyun #define PHY_ID_BCM74371 0xae0252e0 48*4882a593Smuzhiyun #define PHY_ID_BCM7439 0x600d8480 49*4882a593Smuzhiyun #define PHY_ID_BCM7439_2 0xae025080 50*4882a593Smuzhiyun #define PHY_ID_BCM7445 0x600d8510 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define PHY_ID_BCM_CYGNUS 0xae025200 53*4882a593Smuzhiyun #define PHY_ID_BCM_OMEGA 0xae025100 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define PHY_BCM_OUI_MASK 0xfffffc00 56*4882a593Smuzhiyun #define PHY_BCM_OUI_1 0x00206000 57*4882a593Smuzhiyun #define PHY_BCM_OUI_2 0x0143bc00 58*4882a593Smuzhiyun #define PHY_BCM_OUI_3 0x03625c00 59*4882a593Smuzhiyun #define PHY_BCM_OUI_4 0x600d8400 60*4882a593Smuzhiyun #define PHY_BCM_OUI_5 0x03625e00 61*4882a593Smuzhiyun #define PHY_BCM_OUI_6 0xae025000 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun #define PHY_BCM_FLAGS_MODE_COPPER 0x00000001 64*4882a593Smuzhiyun #define PHY_BCM_FLAGS_MODE_1000BX 0x00000002 65*4882a593Smuzhiyun #define PHY_BCM_FLAGS_INTF_SGMII 0x00000010 66*4882a593Smuzhiyun #define PHY_BCM_FLAGS_INTF_XAUI 0x00000020 67*4882a593Smuzhiyun #define PHY_BRCM_WIRESPEED_ENABLE 0x00000100 68*4882a593Smuzhiyun #define PHY_BRCM_AUTO_PWRDWN_ENABLE 0x00000200 69*4882a593Smuzhiyun #define PHY_BRCM_RX_REFCLK_UNUSED 0x00000400 70*4882a593Smuzhiyun #define PHY_BRCM_STD_IBND_DISABLE 0x00000800 71*4882a593Smuzhiyun #define PHY_BRCM_EXT_IBND_RX_ENABLE 0x00001000 72*4882a593Smuzhiyun #define PHY_BRCM_EXT_IBND_TX_ENABLE 0x00002000 73*4882a593Smuzhiyun #define PHY_BRCM_CLEAR_RGMII_MODE 0x00004000 74*4882a593Smuzhiyun #define PHY_BRCM_DIS_TXCRXC_NOENRGY 0x00008000 75*4882a593Smuzhiyun #define PHY_BRCM_EN_MASTER_MODE 0x00010000 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* Broadcom BCM7xxx specific workarounds */ 78*4882a593Smuzhiyun #define PHY_BRCM_7XXX_REV(x) (((x) >> 8) & 0xff) 79*4882a593Smuzhiyun #define PHY_BRCM_7XXX_PATCH(x) ((x) & 0xff) 80*4882a593Smuzhiyun #define PHY_BCM_FLAGS_VALID 0x80000000 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* Broadcom BCM54XX register definitions, common to most Broadcom PHYs */ 83*4882a593Smuzhiyun #define MII_BCM54XX_ECR 0x10 /* BCM54xx extended control register */ 84*4882a593Smuzhiyun #define MII_BCM54XX_ECR_IM 0x1000 /* Interrupt mask */ 85*4882a593Smuzhiyun #define MII_BCM54XX_ECR_IF 0x0800 /* Interrupt force */ 86*4882a593Smuzhiyun #define MII_BCM54XX_ECR_FIFOE 0x0001 /* FIFO elasticity */ 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #define MII_BCM54XX_ESR 0x11 /* BCM54xx extended status register */ 89*4882a593Smuzhiyun #define MII_BCM54XX_ESR_IS 0x1000 /* Interrupt status */ 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun #define MII_BCM54XX_EXP_DATA 0x15 /* Expansion register data */ 92*4882a593Smuzhiyun #define MII_BCM54XX_EXP_SEL 0x17 /* Expansion register select */ 93*4882a593Smuzhiyun #define MII_BCM54XX_EXP_SEL_SSD 0x0e00 /* Secondary SerDes select */ 94*4882a593Smuzhiyun #define MII_BCM54XX_EXP_SEL_ER 0x0f00 /* Expansion register select */ 95*4882a593Smuzhiyun #define MII_BCM54XX_EXP_SEL_ETC 0x0d00 /* Expansion register spare + 2k mem */ 96*4882a593Smuzhiyun 97*4882a593Smuzhiyun #define MII_BCM54XX_AUX_CTL 0x18 /* Auxiliary control register */ 98*4882a593Smuzhiyun #define MII_BCM54XX_ISR 0x1a /* BCM54xx interrupt status register */ 99*4882a593Smuzhiyun #define MII_BCM54XX_IMR 0x1b /* BCM54xx interrupt mask register */ 100*4882a593Smuzhiyun #define MII_BCM54XX_INT_CRCERR 0x0001 /* CRC error */ 101*4882a593Smuzhiyun #define MII_BCM54XX_INT_LINK 0x0002 /* Link status changed */ 102*4882a593Smuzhiyun #define MII_BCM54XX_INT_SPEED 0x0004 /* Link speed change */ 103*4882a593Smuzhiyun #define MII_BCM54XX_INT_DUPLEX 0x0008 /* Duplex mode changed */ 104*4882a593Smuzhiyun #define MII_BCM54XX_INT_LRS 0x0010 /* Local receiver status changed */ 105*4882a593Smuzhiyun #define MII_BCM54XX_INT_RRS 0x0020 /* Remote receiver status changed */ 106*4882a593Smuzhiyun #define MII_BCM54XX_INT_SSERR 0x0040 /* Scrambler synchronization error */ 107*4882a593Smuzhiyun #define MII_BCM54XX_INT_UHCD 0x0080 /* Unsupported HCD negotiated */ 108*4882a593Smuzhiyun #define MII_BCM54XX_INT_NHCD 0x0100 /* No HCD */ 109*4882a593Smuzhiyun #define MII_BCM54XX_INT_NHCDL 0x0200 /* No HCD link */ 110*4882a593Smuzhiyun #define MII_BCM54XX_INT_ANPR 0x0400 /* Auto-negotiation page received */ 111*4882a593Smuzhiyun #define MII_BCM54XX_INT_LC 0x0800 /* All counters below 128 */ 112*4882a593Smuzhiyun #define MII_BCM54XX_INT_HC 0x1000 /* Counter above 32768 */ 113*4882a593Smuzhiyun #define MII_BCM54XX_INT_MDIX 0x2000 /* MDIX status change */ 114*4882a593Smuzhiyun #define MII_BCM54XX_INT_PSERR 0x4000 /* Pair swap error */ 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun #define MII_BCM54XX_SHD 0x1c /* 0x1c shadow registers */ 117*4882a593Smuzhiyun #define MII_BCM54XX_SHD_WRITE 0x8000 118*4882a593Smuzhiyun #define MII_BCM54XX_SHD_VAL(x) ((x & 0x1f) << 10) 119*4882a593Smuzhiyun #define MII_BCM54XX_SHD_DATA(x) ((x & 0x3ff) << 0) 120*4882a593Smuzhiyun 121*4882a593Smuzhiyun #define MII_BCM54XX_RDB_ADDR 0x1e 122*4882a593Smuzhiyun #define MII_BCM54XX_RDB_DATA 0x1f 123*4882a593Smuzhiyun 124*4882a593Smuzhiyun /* legacy access control via rdb/expansion register */ 125*4882a593Smuzhiyun #define BCM54XX_RDB_REG0087 0x0087 126*4882a593Smuzhiyun #define BCM54XX_EXP_REG7E (MII_BCM54XX_EXP_SEL_ER + 0x7E) 127*4882a593Smuzhiyun #define BCM54XX_ACCESS_MODE_LEGACY_EN BIT(15) 128*4882a593Smuzhiyun 129*4882a593Smuzhiyun /* 130*4882a593Smuzhiyun * AUXILIARY CONTROL SHADOW ACCESS REGISTERS. (PHY REG 0x18) 131*4882a593Smuzhiyun */ 132*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_SHDWSEL_AUXCTL 0x00 133*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_ACTL_TX_6DB 0x0400 134*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_ACTL_SMDSP_ENA 0x0800 135*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_ACTL_EXT_PKT_LEN 0x4000 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC 0x07 138*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_WIRESPEED_EN 0x0010 139*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_EN 0x0080 140*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_SHDWSEL_MISC_RGMII_SKEW_EN 0x0100 141*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_MISC_FORCE_AMDIX 0x0200 142*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_MISC_WREN 0x8000 143*4882a593Smuzhiyun 144*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_SHDWSEL_READ_SHIFT 12 145*4882a593Smuzhiyun #define MII_BCM54XX_AUXCTL_SHDWSEL_MASK 0x0007 146*4882a593Smuzhiyun 147*4882a593Smuzhiyun /* 148*4882a593Smuzhiyun * Broadcom LED source encodings. These are used in BCM5461, BCM5481, 149*4882a593Smuzhiyun * BCM5482, and possibly some others. 150*4882a593Smuzhiyun */ 151*4882a593Smuzhiyun #define BCM_LED_SRC_LINKSPD1 0x0 152*4882a593Smuzhiyun #define BCM_LED_SRC_LINKSPD2 0x1 153*4882a593Smuzhiyun #define BCM_LED_SRC_XMITLED 0x2 154*4882a593Smuzhiyun #define BCM_LED_SRC_ACTIVITYLED 0x3 155*4882a593Smuzhiyun #define BCM_LED_SRC_FDXLED 0x4 156*4882a593Smuzhiyun #define BCM_LED_SRC_SLAVE 0x5 157*4882a593Smuzhiyun #define BCM_LED_SRC_INTR 0x6 158*4882a593Smuzhiyun #define BCM_LED_SRC_QUALITY 0x7 159*4882a593Smuzhiyun #define BCM_LED_SRC_RCVLED 0x8 160*4882a593Smuzhiyun #define BCM_LED_SRC_WIRESPEED 0x9 161*4882a593Smuzhiyun #define BCM_LED_SRC_MULTICOLOR1 0xa 162*4882a593Smuzhiyun #define BCM_LED_SRC_OPENSHORT 0xb 163*4882a593Smuzhiyun #define BCM_LED_SRC_OFF 0xe /* Tied high */ 164*4882a593Smuzhiyun #define BCM_LED_SRC_ON 0xf /* Tied low */ 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* 167*4882a593Smuzhiyun * Broadcom Multicolor LED configurations (expansion register 4) 168*4882a593Smuzhiyun */ 169*4882a593Smuzhiyun #define BCM_EXP_MULTICOLOR (MII_BCM54XX_EXP_SEL_ER + 0x04) 170*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_IN_PHASE BIT(8) 171*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_LINK_ACT 0x0 172*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_SPEED 0x1 173*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_ACT_FLASH 0x2 174*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_FDX 0x3 175*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_OFF 0x4 176*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_ON 0x5 177*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_ALT 0x6 178*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_FLASH 0x7 179*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_LINK 0x8 180*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_ACT 0x9 181*4882a593Smuzhiyun #define BCM_LED_MULTICOLOR_PROGRAM 0xa 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* 184*4882a593Smuzhiyun * BCM5482: Shadow registers 185*4882a593Smuzhiyun * Shadow values go into bits [14:10] of register 0x1c to select a shadow 186*4882a593Smuzhiyun * register to access. 187*4882a593Smuzhiyun */ 188*4882a593Smuzhiyun 189*4882a593Smuzhiyun /* 00100: Reserved control register 2 */ 190*4882a593Smuzhiyun #define BCM54XX_SHD_SCR2 0x04 191*4882a593Smuzhiyun #define BCM54XX_SHD_SCR2_WSPD_RTRY_DIS 0x100 192*4882a593Smuzhiyun #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_SHIFT 2 193*4882a593Smuzhiyun #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_OFFSET 2 194*4882a593Smuzhiyun #define BCM54XX_SHD_SCR2_WSPD_RTRY_LMT_MASK 0x7 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* 00101: Spare Control Register 3 */ 197*4882a593Smuzhiyun #define BCM54XX_SHD_SCR3 0x05 198*4882a593Smuzhiyun #define BCM54XX_SHD_SCR3_DEF_CLK125 0x0001 199*4882a593Smuzhiyun #define BCM54XX_SHD_SCR3_DLLAPD_DIS 0x0002 200*4882a593Smuzhiyun #define BCM54XX_SHD_SCR3_TRDDAPD 0x0004 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun /* 01010: Auto Power-Down */ 203*4882a593Smuzhiyun #define BCM54XX_SHD_APD 0x0a 204*4882a593Smuzhiyun #define BCM_APD_CLR_MASK 0xFE9F /* clear bits 5, 6 & 8 */ 205*4882a593Smuzhiyun #define BCM54XX_SHD_APD_EN 0x0020 206*4882a593Smuzhiyun #define BCM_NO_ANEG_APD_EN 0x0060 /* bits 5 & 6 */ 207*4882a593Smuzhiyun #define BCM_APD_SINGLELP_EN 0x0100 /* Bit 8 */ 208*4882a593Smuzhiyun 209*4882a593Smuzhiyun #define BCM5482_SHD_LEDS1 0x0d /* 01101: LED Selector 1 */ 210*4882a593Smuzhiyun /* LED3 / ~LINKSPD[2] selector */ 211*4882a593Smuzhiyun #define BCM5482_SHD_LEDS1_LED3(src) ((src & 0xf) << 4) 212*4882a593Smuzhiyun /* LED1 / ~LINKSPD[1] selector */ 213*4882a593Smuzhiyun #define BCM5482_SHD_LEDS1_LED1(src) ((src & 0xf) << 0) 214*4882a593Smuzhiyun #define BCM54XX_SHD_RGMII_MODE 0x0b /* 01011: RGMII Mode Selector */ 215*4882a593Smuzhiyun #define BCM5482_SHD_SSD 0x14 /* 10100: Secondary SerDes control */ 216*4882a593Smuzhiyun #define BCM5482_SHD_SSD_LEDM 0x0008 /* SSD LED Mode enable */ 217*4882a593Smuzhiyun #define BCM5482_SHD_SSD_EN 0x0001 /* SSD enable */ 218*4882a593Smuzhiyun 219*4882a593Smuzhiyun /* 10011: SerDes 100-FX Control Register */ 220*4882a593Smuzhiyun #define BCM54616S_SHD_100FX_CTRL 0x13 221*4882a593Smuzhiyun #define BCM54616S_100FX_MODE BIT(0) /* 100-FX SerDes Enable */ 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* 11111: Mode Control Register */ 224*4882a593Smuzhiyun #define BCM54XX_SHD_MODE 0x1f 225*4882a593Smuzhiyun #define BCM54XX_SHD_INTF_SEL_MASK GENMASK(2, 1) /* INTERF_SEL[1:0] */ 226*4882a593Smuzhiyun #define BCM54XX_SHD_INTF_SEL_RGMII 0x02 227*4882a593Smuzhiyun #define BCM54XX_SHD_INTF_SEL_SGMII 0x04 228*4882a593Smuzhiyun #define BCM54XX_SHD_INTF_SEL_GBIC 0x06 229*4882a593Smuzhiyun #define BCM54XX_SHD_MODE_1000BX BIT(0) /* Enable 1000-X registers */ 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* 232*4882a593Smuzhiyun * EXPANSION SHADOW ACCESS REGISTERS. (PHY REG 0x15, 0x16, and 0x17) 233*4882a593Smuzhiyun */ 234*4882a593Smuzhiyun #define MII_BCM54XX_EXP_AADJ1CH0 0x001f 235*4882a593Smuzhiyun #define MII_BCM54XX_EXP_AADJ1CH0_SWP_ABCD_OEN 0x0200 236*4882a593Smuzhiyun #define MII_BCM54XX_EXP_AADJ1CH0_SWSEL_THPF 0x0100 237*4882a593Smuzhiyun #define MII_BCM54XX_EXP_AADJ1CH3 0x601f 238*4882a593Smuzhiyun #define MII_BCM54XX_EXP_AADJ1CH3_ADCCKADJ 0x0002 239*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP08 0x0F08 240*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP08_RJCT_2MHZ 0x0001 241*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP08_EARLY_DAC_WAKE 0x0200 242*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP75 0x0f75 243*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP75_VDACCTRL 0x003c 244*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP75_CM_OSC 0x0001 245*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP96 0x0f96 246*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP96_MYST 0x0010 247*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP97 0x0f97 248*4882a593Smuzhiyun #define MII_BCM54XX_EXP_EXP97_MYST 0x0c0c 249*4882a593Smuzhiyun 250*4882a593Smuzhiyun /* 251*4882a593Smuzhiyun * BCM5482: Secondary SerDes registers 252*4882a593Smuzhiyun */ 253*4882a593Smuzhiyun #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */ 254*4882a593Smuzhiyun #define BCM5482_SSD_1000BX_CTL_PWRDOWN 0x0800 /* Power-down SSD */ 255*4882a593Smuzhiyun #define BCM5482_SSD_SGMII_SLAVE 0x15 /* SGMII Slave Register */ 256*4882a593Smuzhiyun #define BCM5482_SSD_SGMII_SLAVE_EN 0x0002 /* Slave mode enable */ 257*4882a593Smuzhiyun #define BCM5482_SSD_SGMII_SLAVE_AD 0x0001 /* Slave auto-detection */ 258*4882a593Smuzhiyun 259*4882a593Smuzhiyun /* BCM54810 Registers */ 260*4882a593Smuzhiyun #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL (MII_BCM54XX_EXP_SEL_ER + 0x90) 261*4882a593Smuzhiyun #define BCM54810_EXP_BROADREACH_LRE_MISC_CTL_EN (1 << 0) 262*4882a593Smuzhiyun #define BCM54810_SHD_CLK_CTL 0x3 263*4882a593Smuzhiyun #define BCM54810_SHD_CLK_CTL_GTXCLK_EN (1 << 9) 264*4882a593Smuzhiyun #define BCM54810_SHD_SCR3_TRDDAPD 0x0100 265*4882a593Smuzhiyun 266*4882a593Smuzhiyun /* BCM54612E Registers */ 267*4882a593Smuzhiyun #define BCM54612E_EXP_SPARE0 (MII_BCM54XX_EXP_SEL_ETC + 0x34) 268*4882a593Smuzhiyun #define BCM54612E_LED4_CLK125OUT_EN (1 << 1) 269*4882a593Smuzhiyun 270*4882a593Smuzhiyun /*****************************************************************************/ 271*4882a593Smuzhiyun /* Fast Ethernet Transceiver definitions. */ 272*4882a593Smuzhiyun /*****************************************************************************/ 273*4882a593Smuzhiyun 274*4882a593Smuzhiyun #define MII_BRCM_FET_INTREG 0x1a /* Interrupt register */ 275*4882a593Smuzhiyun #define MII_BRCM_FET_IR_MASK 0x0100 /* Mask all interrupts */ 276*4882a593Smuzhiyun #define MII_BRCM_FET_IR_LINK_EN 0x0200 /* Link status change enable */ 277*4882a593Smuzhiyun #define MII_BRCM_FET_IR_SPEED_EN 0x0400 /* Link speed change enable */ 278*4882a593Smuzhiyun #define MII_BRCM_FET_IR_DUPLEX_EN 0x0800 /* Duplex mode change enable */ 279*4882a593Smuzhiyun #define MII_BRCM_FET_IR_ENABLE 0x4000 /* Interrupt enable */ 280*4882a593Smuzhiyun 281*4882a593Smuzhiyun #define MII_BRCM_FET_BRCMTEST 0x1f /* Brcm test register */ 282*4882a593Smuzhiyun #define MII_BRCM_FET_BT_SRE 0x0080 /* Shadow register enable */ 283*4882a593Smuzhiyun 284*4882a593Smuzhiyun 285*4882a593Smuzhiyun /*** Shadow register definitions ***/ 286*4882a593Smuzhiyun 287*4882a593Smuzhiyun #define MII_BRCM_FET_SHDW_MISCCTRL 0x10 /* Shadow misc ctrl */ 288*4882a593Smuzhiyun #define MII_BRCM_FET_SHDW_MC_FAME 0x4000 /* Force Auto MDIX enable */ 289*4882a593Smuzhiyun 290*4882a593Smuzhiyun #define MII_BRCM_FET_SHDW_AUXMODE4 0x1a /* Auxiliary mode 4 */ 291*4882a593Smuzhiyun #define MII_BRCM_FET_SHDW_AM4_LED_MASK 0x0003 292*4882a593Smuzhiyun #define MII_BRCM_FET_SHDW_AM4_LED_MODE1 0x0001 293*4882a593Smuzhiyun 294*4882a593Smuzhiyun #define MII_BRCM_FET_SHDW_AUXSTAT2 0x1b /* Auxiliary status 2 */ 295*4882a593Smuzhiyun #define MII_BRCM_FET_SHDW_AS2_APDE 0x0020 /* Auto power down enable */ 296*4882a593Smuzhiyun 297*4882a593Smuzhiyun #define BRCM_CL45VEN_EEE_CONTROL 0x803d 298*4882a593Smuzhiyun #define LPI_FEATURE_EN 0x8000 299*4882a593Smuzhiyun #define LPI_FEATURE_EN_DIG1000X 0x4000 300*4882a593Smuzhiyun 301*4882a593Smuzhiyun /* Core register definitions*/ 302*4882a593Smuzhiyun #define MII_BRCM_CORE_BASE12 0x12 303*4882a593Smuzhiyun #define MII_BRCM_CORE_BASE13 0x13 304*4882a593Smuzhiyun #define MII_BRCM_CORE_BASE14 0x14 305*4882a593Smuzhiyun #define MII_BRCM_CORE_BASE1E 0x1E 306*4882a593Smuzhiyun #define MII_BRCM_CORE_EXPB0 0xB0 307*4882a593Smuzhiyun #define MII_BRCM_CORE_EXPB1 0xB1 308*4882a593Smuzhiyun 309*4882a593Smuzhiyun /* Enhanced Cable Diagnostics */ 310*4882a593Smuzhiyun #define BCM54XX_RDB_ECD_CTRL 0x2a0 311*4882a593Smuzhiyun #define BCM54XX_EXP_ECD_CTRL (MII_BCM54XX_EXP_SEL_ER + 0xc0) 312*4882a593Smuzhiyun 313*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT3 1 /* CAT3 or worse */ 314*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_CABLE_TYPE_CAT5 0 /* CAT5 or better */ 315*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_CABLE_TYPE_MASK BIT(0) /* cable type */ 316*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_INVALID BIT(3) /* invalid result */ 317*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_UNIT_CM 0 /* centimeters */ 318*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_UNIT_M 1 /* meters */ 319*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_UNIT_MASK BIT(10) /* cable length unit */ 320*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_IN_PROGRESS BIT(11) /* test in progress */ 321*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_BREAK_LINK BIT(12) /* unconnect link 322*4882a593Smuzhiyun * during test 323*4882a593Smuzhiyun */ 324*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_CROSS_SHORT_DIS BIT(13) /* disable inter-pair 325*4882a593Smuzhiyun * short check 326*4882a593Smuzhiyun */ 327*4882a593Smuzhiyun #define BCM54XX_ECD_CTRL_RUN BIT(15) /* run immediate */ 328*4882a593Smuzhiyun 329*4882a593Smuzhiyun #define BCM54XX_RDB_ECD_FAULT_TYPE 0x2a1 330*4882a593Smuzhiyun #define BCM54XX_EXP_ECD_FAULT_TYPE (MII_BCM54XX_EXP_SEL_ER + 0xc1) 331*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_INVALID 0x0 332*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_OK 0x1 333*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_OPEN 0x2 334*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_SAME_SHORT 0x3 /* short same pair */ 335*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_CROSS_SHORT 0x4 /* short different pairs */ 336*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_BUSY 0x9 337*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_PAIR_D_MASK GENMASK(3, 0) 338*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_PAIR_C_MASK GENMASK(7, 4) 339*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_PAIR_B_MASK GENMASK(11, 8) 340*4882a593Smuzhiyun #define BCM54XX_ECD_FAULT_TYPE_PAIR_A_MASK GENMASK(15, 12) 341*4882a593Smuzhiyun #define BCM54XX_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 342*4882a593Smuzhiyun #define BCM54XX_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 343*4882a593Smuzhiyun #define BCM54XX_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 344*4882a593Smuzhiyun #define BCM54XX_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 345*4882a593Smuzhiyun 346*4882a593Smuzhiyun #define BCM54XX_RDB_ECD_PAIR_A_LENGTH_RESULTS 0x2a2 347*4882a593Smuzhiyun #define BCM54XX_EXP_ECD_PAIR_A_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc2) 348*4882a593Smuzhiyun #define BCM54XX_RDB_ECD_PAIR_B_LENGTH_RESULTS 0x2a3 349*4882a593Smuzhiyun #define BCM54XX_EXP_ECD_PAIR_B_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc3) 350*4882a593Smuzhiyun #define BCM54XX_RDB_ECD_PAIR_C_LENGTH_RESULTS 0x2a4 351*4882a593Smuzhiyun #define BCM54XX_EXP_ECD_PAIR_C_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc4) 352*4882a593Smuzhiyun #define BCM54XX_RDB_ECD_PAIR_D_LENGTH_RESULTS 0x2a5 353*4882a593Smuzhiyun #define BCM54XX_EXP_ECD_PAIR_D_LENGTH_RESULTS (MII_BCM54XX_EXP_SEL_ER + 0xc5) 354*4882a593Smuzhiyun #define BCM54XX_ECD_LENGTH_RESULTS_INVALID 0xffff 355*4882a593Smuzhiyun 356*4882a593Smuzhiyun #endif /* _LINUX_BRCMPHY_H */ 357