1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* linux/amba/pl093.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2008 Simtec Electronics 5*4882a593Smuzhiyun * http://armlinux.simtec.co.uk/ 6*4882a593Smuzhiyun * Ben Dooks <ben@simtec.co.uk> 7*4882a593Smuzhiyun * 8*4882a593Smuzhiyun * AMBA PL093 SSMC (synchronous static memory controller) 9*4882a593Smuzhiyun * See DDI0236.pdf (r0p4) for more details 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #define SMB_BANK(x) ((x) * 0x20) /* each bank control set is 0x20 apart */ 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun /* Offsets for SMBxxxxRy registers */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun #define SMBIDCYR (0x00) 17*4882a593Smuzhiyun #define SMBWSTRDR (0x04) 18*4882a593Smuzhiyun #define SMBWSTWRR (0x08) 19*4882a593Smuzhiyun #define SMBWSTOENR (0x0C) 20*4882a593Smuzhiyun #define SMBWSTWENR (0x10) 21*4882a593Smuzhiyun #define SMBCR (0x14) 22*4882a593Smuzhiyun #define SMBSR (0x18) 23*4882a593Smuzhiyun #define SMBWSTBRDR (0x1C) 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Masks for SMB registers */ 26*4882a593Smuzhiyun #define IDCY_MASK (0xf) 27*4882a593Smuzhiyun #define WSTRD_MASK (0xf) 28*4882a593Smuzhiyun #define WSTWR_MASK (0xf) 29*4882a593Smuzhiyun #define WSTOEN_MASK (0xf) 30*4882a593Smuzhiyun #define WSTWEN_MASK (0xf) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Notes from datasheet: 33*4882a593Smuzhiyun * WSTOEN <= WSTRD 34*4882a593Smuzhiyun * WSTWEN <= WSTWR 35*4882a593Smuzhiyun * 36*4882a593Smuzhiyun * WSTOEN is not used with nWAIT 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* SMBCR bit definitions */ 40*4882a593Smuzhiyun #define SMBCR_BIWRITEEN (1 << 21) 41*4882a593Smuzhiyun #define SMBCR_ADDRVALIDWRITEEN (1 << 20) 42*4882a593Smuzhiyun #define SMBCR_SYNCWRITE (1 << 17) 43*4882a593Smuzhiyun #define SMBCR_BMWRITE (1 << 16) 44*4882a593Smuzhiyun #define SMBCR_WRAPREAD (1 << 14) 45*4882a593Smuzhiyun #define SMBCR_BIREADEN (1 << 13) 46*4882a593Smuzhiyun #define SMBCR_ADDRVALIDREADEN (1 << 12) 47*4882a593Smuzhiyun #define SMBCR_SYNCREAD (1 << 9) 48*4882a593Smuzhiyun #define SMBCR_BMREAD (1 << 8) 49*4882a593Smuzhiyun #define SMBCR_SMBLSPOL (1 << 6) 50*4882a593Smuzhiyun #define SMBCR_WP (1 << 3) 51*4882a593Smuzhiyun #define SMBCR_WAITEN (1 << 2) 52*4882a593Smuzhiyun #define SMBCR_WAITPOL (1 << 1) 53*4882a593Smuzhiyun #define SMBCR_RBLE (1 << 0) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define SMBCR_BURSTLENWRITE_MASK (3 << 18) 56*4882a593Smuzhiyun #define SMBCR_BURSTLENWRITE_4 (0 << 18) 57*4882a593Smuzhiyun #define SMBCR_BURSTLENWRITE_8 (1 << 18) 58*4882a593Smuzhiyun #define SMBCR_BURSTLENWRITE_RESERVED (2 << 18) 59*4882a593Smuzhiyun #define SMBCR_BURSTLENWRITE_CONTINUOUS (3 << 18) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define SMBCR_BURSTLENREAD_MASK (3 << 10) 62*4882a593Smuzhiyun #define SMBCR_BURSTLENREAD_4 (0 << 10) 63*4882a593Smuzhiyun #define SMBCR_BURSTLENREAD_8 (1 << 10) 64*4882a593Smuzhiyun #define SMBCR_BURSTLENREAD_16 (2 << 10) 65*4882a593Smuzhiyun #define SMBCR_BURSTLENREAD_CONTINUOUS (3 << 10) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define SMBCR_MW_MASK (3 << 4) 68*4882a593Smuzhiyun #define SMBCR_MW_8BIT (0 << 4) 69*4882a593Smuzhiyun #define SMBCR_MW_16BIT (1 << 4) 70*4882a593Smuzhiyun #define SMBCR_MW_M32BIT (2 << 4) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun /* SSMC status registers */ 73*4882a593Smuzhiyun #define SSMCCSR (0x200) 74*4882a593Smuzhiyun #define SSMCCR (0x204) 75*4882a593Smuzhiyun #define SSMCITCR (0x208) 76*4882a593Smuzhiyun #define SSMCITIP (0x20C) 77*4882a593Smuzhiyun #define SSMCITIOP (0x210) 78