1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-or-later */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * linux/include/asm-arm/hardware/amba_kmi.h 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Internal header file for AMBA KMI ports 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Copyright (C) 2000 Deep Blue Solutions Ltd. 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * --------------------------------------------------------------------------- 10*4882a593Smuzhiyun * From ARM PrimeCell(tm) PS2 Keyboard/Mouse Interface (PL050) Technical 11*4882a593Smuzhiyun * Reference Manual - ARM DDI 0143B - see http://www.arm.com/ 12*4882a593Smuzhiyun * --------------------------------------------------------------------------- 13*4882a593Smuzhiyun */ 14*4882a593Smuzhiyun #ifndef ASM_ARM_HARDWARE_AMBA_KMI_H 15*4882a593Smuzhiyun #define ASM_ARM_HARDWARE_AMBA_KMI_H 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* 18*4882a593Smuzhiyun * KMI control register: 19*4882a593Smuzhiyun * KMICR_TYPE 0 = PS2/AT mode, 1 = No line control bit mode 20*4882a593Smuzhiyun * KMICR_RXINTREN 1 = enable RX interrupts 21*4882a593Smuzhiyun * KMICR_TXINTREN 1 = enable TX interrupts 22*4882a593Smuzhiyun * KMICR_EN 1 = enable KMI 23*4882a593Smuzhiyun * KMICR_FD 1 = force KMI data low 24*4882a593Smuzhiyun * KMICR_FC 1 = force KMI clock low 25*4882a593Smuzhiyun */ 26*4882a593Smuzhiyun #define KMICR (KMI_BASE + 0x00) 27*4882a593Smuzhiyun #define KMICR_TYPE (1 << 5) 28*4882a593Smuzhiyun #define KMICR_RXINTREN (1 << 4) 29*4882a593Smuzhiyun #define KMICR_TXINTREN (1 << 3) 30*4882a593Smuzhiyun #define KMICR_EN (1 << 2) 31*4882a593Smuzhiyun #define KMICR_FD (1 << 1) 32*4882a593Smuzhiyun #define KMICR_FC (1 << 0) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* 35*4882a593Smuzhiyun * KMI status register: 36*4882a593Smuzhiyun * KMISTAT_TXEMPTY 1 = transmitter register empty 37*4882a593Smuzhiyun * KMISTAT_TXBUSY 1 = currently sending data 38*4882a593Smuzhiyun * KMISTAT_RXFULL 1 = receiver register ready to be read 39*4882a593Smuzhiyun * KMISTAT_RXBUSY 1 = currently receiving data 40*4882a593Smuzhiyun * KMISTAT_RXPARITY parity of last databyte received 41*4882a593Smuzhiyun * KMISTAT_IC current level of KMI clock input 42*4882a593Smuzhiyun * KMISTAT_ID current level of KMI data input 43*4882a593Smuzhiyun */ 44*4882a593Smuzhiyun #define KMISTAT (KMI_BASE + 0x04) 45*4882a593Smuzhiyun #define KMISTAT_TXEMPTY (1 << 6) 46*4882a593Smuzhiyun #define KMISTAT_TXBUSY (1 << 5) 47*4882a593Smuzhiyun #define KMISTAT_RXFULL (1 << 4) 48*4882a593Smuzhiyun #define KMISTAT_RXBUSY (1 << 3) 49*4882a593Smuzhiyun #define KMISTAT_RXPARITY (1 << 2) 50*4882a593Smuzhiyun #define KMISTAT_IC (1 << 1) 51*4882a593Smuzhiyun #define KMISTAT_ID (1 << 0) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun /* 54*4882a593Smuzhiyun * KMI data register 55*4882a593Smuzhiyun */ 56*4882a593Smuzhiyun #define KMIDATA (KMI_BASE + 0x08) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* 59*4882a593Smuzhiyun * KMI clock divisor: to generate 8MHz internal clock 60*4882a593Smuzhiyun * div = (ref / 8MHz) - 1; 0 <= div <= 15 61*4882a593Smuzhiyun */ 62*4882a593Smuzhiyun #define KMICLKDIV (KMI_BASE + 0x0c) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* 65*4882a593Smuzhiyun * KMI interrupt register: 66*4882a593Smuzhiyun * KMIIR_TXINTR 1 = transmit interrupt asserted 67*4882a593Smuzhiyun * KMIIR_RXINTR 1 = receive interrupt asserted 68*4882a593Smuzhiyun */ 69*4882a593Smuzhiyun #define KMIIR (KMI_BASE + 0x10) 70*4882a593Smuzhiyun #define KMIIR_TXINTR (1 << 1) 71*4882a593Smuzhiyun #define KMIIR_RXINTR (1 << 0) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun /* 74*4882a593Smuzhiyun * The size of the KMI primecell 75*4882a593Smuzhiyun */ 76*4882a593Smuzhiyun #define KMI_SIZE (0x100) 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun #endif 79